公开(公告)号：US10354951B1

公开(公告)日：2019-07-16

申请号：US15872429

申请日：2018-01-16

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L21/768 ,  H01L23/522 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L28/24

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US20190019858A1

公开(公告)日：2019-01-17

申请号：US15646917

申请日：2017-07-11

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A device and method for fabricating an integrated circuit (IC) chip is disclosed. The method includes depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; and patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor. The method continues with depositing a second ILD layer overlying the first resistor; and patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor. The etch retardant layer is selective to a first etch chemistry and the thickness of the etch retardant layer is such that the via etching process removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material.

公开(公告)号：US09460962B1

公开(公告)日：2016-10-04

申请号：US14820542

申请日：2015-08-06

Applicant: Texas Instruments Incorporated

Inventor： David William Hamann ,  Thomas E. Lillibridge ,  Abbas Ali

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L29/408 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/743 ,  H01L29/0623 ,  H01L29/401 ,  H01L29/407

Abstract: A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step process forms a protective polymer on an existing top surface of the semiconductor device, and on the dielectric liner proximate to a top surface of the substrate. The pre-etch deposition step does not remove a significant amount of the dielectric liner from the bottom of the deep trench. A main etch step of the two-step process removes the dielectric liner at the bottom of the deep trench while maintaining the protective polymer at the top of the deep trench. The protective polymer is subsequently removed.

Abstract translation: 具有深沟槽的半导体器件具有形成在深沟槽的侧壁和底部上的电介质衬垫。 两步法的预蚀刻沉积步骤在半导体器件的现有顶表面上以及靠近衬底顶表面的电介质衬垫上形成保护性聚合物。 预蚀刻沉积步骤不会从深沟槽的底部去除大量的电介质衬垫。 两步法的主蚀刻步骤除去深沟槽底部的电介质衬垫，同时将保护性聚合物保持在深沟槽的顶部。 随后除去保护性聚合物。

公开(公告)号：US20150072443A1

公开(公告)日：2015-03-12

申请号：US14473768

申请日：2014-08-29

Applicant: Texas Instruments Incorporated

Inventor： John Christopher Shriner ,  Abbas Ali

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/02197 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L22/26 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

Abstract: A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF4. Endpoint detection can be used to detect the point at which the upper plate etch reaches the PZT, at which point the gases in the chamber are purged to avoid etching the PZT material with fluorine. A steeper sidewall angle for the capacitor structure can be obtained.

Abstract translation: 一种用诸如钛酸锆（PZT）之类的铁电材料的导电上板和下板蚀刻铁电电容器堆叠结构的方法，其中每个层由同一硬掩模元件限定。 堆叠蚀刻工艺包括在导电板的蚀刻中具有含氟物质作为活性物质的等离子体蚀刻和用于蚀刻PZT铁电材料的非含氟化学物质。 含氟物质的实例是CF 4。 可以使用端点检测来检测上板蚀刻到达PZT的点，此时，腔中的气体被清除以避免用氟蚀刻PZT材料。 可以获得电容器结构的更陡的侧壁角。

公开(公告)号：US20240258175A1

公开(公告)日：2024-08-01

申请号：US18632439

申请日：2024-04-11

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823462 ,  H01L27/088

Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

公开(公告)号：US20240258112A1

公开(公告)日：2024-08-01

申请号：US18103134

申请日：2023-01-30

Applicant: Texas Instruments Incorporated

Inventor： Chao Zuo ,  Jing Hu ,  Tian Ping Lv ,  Abbas Ali ,  Manoj K Jain

IPC: H01L21/3065

CPC classification number: H01L21/30655 ,  H01L28/40

Abstract: A method of forming an integrated circuit includes forming a plurality of openings in a resist layer over a semiconductor substrate and removing portions of a semiconductor surface layer exposed by the openings, thereby forming a plurality of deep trenches. Removing the portions includes performing a first etch loop for a first plurality of repetitions, the first etch loop including a deposition process executed for a first deposition time and an etch process executed for a first etch time. The removing further includes performing a second etch loop for a second plurality of repetitions, the second etch loop including the deposition process executed for a second deposition time and an etch process executed for a second etch time. The second deposition time is at least 10% greater than the first deposition time, and the second etch time is at least 10% greater than the first etch time.

公开(公告)号：US11942359B2

公开(公告)日：2024-03-26

申请号：US17538372

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  Brian K. Kirkpatrick ,  Byron Joseph Palla

IPC: H01L21/762 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/76202 ,  H01L27/0203 ,  H01L29/0649

Abstract: Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.

公开(公告)号：US20230215737A1

公开(公告)日：2023-07-06

申请号：US17566942

申请日：2021-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  Pushpa Mahalingam ,  Uma Aghoram ,  Eddie Dee Pylant

IPC: H01L21/322

CPC classification number: H01L21/322 ,  H01L21/76224

Abstract: A method of forming an integrated circuit that includes placing a semiconductor substrate in a process chamber at an initial temperature, wherein one or more trenches are located within the semiconductor substrate. The temperature of the substrate is increased in a substantially oxygen-free ambient to an oxide-growth temperature. The temperature is then maintained at the oxide growth temperature while providing an oxidizing ambient, thereby forming an oxide layer on sidewalls of the trench. The temperature of the semiconductor wafer is then reduced to a final temperature below the initial temperature and removed from the process chamber.

公开(公告)号：US20230126899A1

公开(公告)日：2023-04-27

申请号：US17512534

申请日：2021-10-27

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Scott Hiemke

IPC: H01L21/74 ,  H01L49/02 ,  H01L21/762 ,  H01L23/58

Abstract: A microelectronic device includes an integrated deep trench in a substrate, with a field oxide layer on the substrate. The integrated deep trench includes a of deep trench extending into semiconductor material of the substrate, a deep trench sidewall dielectric layer contacting the substrate and an electrically conductive trench-fill material contacting the deep trench sidewall dielectric layer. The conductive trench-fill material is covered during the formation of the field oxide layer to minimize the trench-fill seam void volume. Minimizing the trench-fill seam void volume minimizes optical defectivity observed in subsequent yield enhancement. The integrated deep trench may be configured as a capacitor or may be configured as a contact to the underlying substrate.

公开(公告)号：US11239230B2

公开(公告)日：2022-02-01

申请号：US16665288

申请日：2019-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Guruvayurappan Mathur ,  Poornika Fernandes

IPC: H01L27/07 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06

Abstract: An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.