公开(公告)号：US11152904B2

公开(公告)日：2021-10-19

申请号：US16789540

申请日：2020-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Subramanian ,  Tanmay Halder ,  Anand Kannan

IPC: H03F3/45 ,  H03G3/30 ,  H03M1/12

Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

公开(公告)号：US10763889B1

公开(公告)日：2020-09-01

申请号：US16661456

申请日：2019-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Uttam Kumar Agarwal ,  Anand Kannan ,  Ramamurthy Vishweshwara ,  Anand Subramanian ,  Pedro Ramon Gelabert ,  Diljith Mathal Thodi ,  Abhijit Anant Patki

IPC: H03M3/00 ,  H03G3/00 ,  H03G1/00 ,  H03G3/30 ,  H03M7/34 ,  H03M1/12 ,  H03M1/06 ,  H03G5/02

Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.

公开(公告)号：US10747249B1

公开(公告)日：2020-08-18

申请号：US16448928

申请日：2019-06-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Subramanian ,  Anand Kannan

IPC: G05F1/575 ,  H03H7/06 ,  H03M1/12

Abstract: A system includes: a reference buffer coupled to an input supply voltage; an analog-to-digital converter (ADC) coupled to an output of the reference buffer; and an output capacitor coupled between the output of the reference buffer and a ground node. The reference buffer includes: an integrator; an internal capacitor coupled between an output of the integrator and the ground node; a first gain stage with an input coupled to the output of the reference buffer; and a second gain stage with an input coupled to the output of the integrator. The output of the first gain stage is combined with the output of the integrator using a combine circuit.

公开(公告)号：US20180239383A1

公开(公告)日：2018-08-23

申请号：US15962515

申请日：2018-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Praful Kumar Parakh ,  Anand Kannan ,  Sunil Rafeeque

IPC: G05F3/24

CPC classification number: G05F3/245

Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

公开(公告)号：US20150084797A1

公开(公告)日：2015-03-26

申请号：US14033047

申请日：2013-09-20

Applicant: Texas Instruments Incorporated

Inventor： Vikas Singh ,  Anand Kannan ,  Ashish Lachhwani

IPC: H03M3/00 ,  H03M1/46 ,  H03M1/00

CPC classification number: H03M3/372 ,  H03M1/002 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/454

Abstract: A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.

Abstract translation: 具有输入级和输出级的Δ-Σ调制器。 输入级接收模拟输入信号和第一数模转换器（DAC）的输出。 输入级产生处理后的误差信号。 附加求和装置接收处理的误差信号。 输出级接收附加求和装置的输出并产生延迟的数字输出信号。 差分器和第一个数模转换器（DAC）接收延迟的数字输出信号作为反馈信号。 第二DAC接收微分器的输出，并向另外的负反馈系数乘法器提供输出。 附加求和装置接收附加负反馈系数乘法器的输出。

公开(公告)号：US20130229306A1

公开(公告)日：2013-09-05

申请号：US13850802

申请日：2013-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saravana Kumar Ganeshan ,  Bijoy Bhukania ,  Anand Kannan

IPC: G01S19/33

CPC classification number: G01S19/33 ,  G01S19/37 ,  H04B1/0085

Abstract: A wireless receiver for multiple frequency bands reception includes a single receive radio frequency (RF) circuit (160, 170) having an RF bandpass substantially confined to encompass at least two non-overlapped such frequency bands at RF, a single in-phase and quadrature (approximately I, Q) pair of intermediate frequency (IF) sections (120I, 120Q) having an IF passband, and a mixer circuit (110) including an in-phase and quadrature (I,Q) pair of mixers (110I, 110Q) fed by said RF circuit (160, 170) and having a local oscillator (100) with in-phase and quadrature outputs coupled to said mixers (110I, 110Q) respectively, said mixer circuit (110) operable to inject and substantially overlap the at least two non-overlapped frequency bands with each other into the IQ IF sections (120I, 120Q) in the IF passband, the IF passband substantially confined to a bandwidth encompassing the thereby-overlapped frequency bands.

Abstract translation: 用于多个频带接收的无线接收器包括具有RF带通的单个接收射频（RF）电路（160,170），其基本上限制为在RF处包含至少两个非重叠的这样的频带，单个同相和正交 具有IF通带的中频（IFI）部分（IFI）部分（120I，120Q）以及包括同相和正交（I，Q）对混频器（110I，110Q）的混频器电路 ），并且具有分别耦合到所述混频器（110I，110Q）的同相和正交输出的本地振荡器（100），所述混频器电路（110）可操作地注入并基本上重叠 至少两个非重叠频带彼此分配到IF通带中的IQ IF部分（120I，120Q）中，IF通带基本上限于包含由此重叠的频带的带宽。

公开(公告)号：US10911004B2

公开(公告)日：2021-02-02

申请号：US16450101

申请日：2019-06-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Subramanian ,  Anand Kannan

IPC: H03F3/45 ,  H03F1/26 ,  H03F3/68 ,  H03F1/34

Abstract: A chopper-stabilized amplifier includes a first transconductance amplifier and a first chopper circuit coupled to an input of the first transconductance amplifier. A second chopper circuit is coupled to an output of the first transconductance amplifier. The chopper-stabilized amplifier also includes second and third transconductance amplifiers having inputs coupled to the output of the first transconductance amplifier. The second transconductance amplifier produces an output responsive to a first notch clock signal having a first phase relative to the chopping of the second chopper circuit. The third transconductance amplifier produces an output responsive to a second notch clock signal having a second phase relative to the first phase. The output signals produced by the second and third transconductance amplifiers are added to filter ripple noise at the outputs of the second and third transconductance amplifiers.

公开(公告)号：US10892770B2

公开(公告)日：2021-01-12

申请号：US16668744

申请日：2019-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tanmay Halder ,  Anand Kannan

IPC: H03M1/66 ,  H03M1/44 ,  H03M1/12 ,  H03M3/00 ,  H03M1/00

Abstract: Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.

公开(公告)号：US10680608B2

公开(公告)日：2020-06-09

申请号：US15231350

申请日：2016-08-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Priyank Anand ,  Anand Kannan ,  Venkatesh Guduri

IPC: H03K17/00 ,  H03K17/693 ,  H03K17/16

Abstract: A multiplexer comprises: a first switch; a second switch; a dummy component coupled to the first switch and the second switch and configured to: reduce a first charge injection of the first switch, and reduce a second charge injection of the second switch; and an output coupled to the first switch, the second switch, and the dummy component. A method comprises: providing an output from either a first switch or a second switch; coupling, by a dummy component, to the first switch and the second switch; using a BBM action; and reducing, by the dummy component, a first charge injection of the first switch or a second charge injection of the second switch.

公开(公告)号：US08604974B2

公开(公告)日：2013-12-10

申请号：US13850802

申请日：2013-03-26

Applicant: Texas Instruments Incorporated

Inventor： Saravana Kumar Ganeshan ,  Bijoy Bhukania ,  Anand Kannan

IPC: G01S19/33

CPC classification number: G01S19/33 ,  G01S19/37 ,  H04B1/0085

Abstract: An electronic circuit separates frequency-overlapped GLONASS and GPS overlapped in an approximately 4 MHz passband. The circuit uses a multiple-path analog-to-digital converter circuit (ADC). A sampling rate circuit is coupled to concurrently operate the analog-to-digital converter circuit at a sampling rate between about 60 Msps and about 80 Msps. A digital processing circuit includes storage defining complex de-rotation and low pass filtering. The digital processing circuit is fed by the analog-to-digital converter circuit and is operable A) to establish an access rate and respective distinct phase increments for the complex de-rotation, B) to execute the complex de-rotation by combinations of trigonometric multiplications using the distinct phase increments approximately concurrently and C) to execute the low pass filtering on the complex de-rotation resulting at the access rate and respective distinct phase increments, thus delivering GPS and Glonass signals separated from each other.

Abstract translation: 电子电路将频率重叠的GLONASS和GPS重叠在大约4MHz的通带中。 该电路使用多通道模数转换器电路（ADC）。 耦合采样率电路以以约60 Msps至约80 Msps的采样率并行操作模数转换器电路。 数字处理电路包括定义复数去旋转和低通滤波的存储器。 数字处理电路由模拟 - 数字转换器电路馈送并且可操作地A）建立访问速率和用于复位去旋转的相应的不同相位增量，B）通过三角形的组合来执行复数去旋转 使用不同相位增量大致并行地进行乘法，并且C）对复数去旋转执行低通滤波，导致访问速率和相应的不同相位增量，从而传送彼此分离的GPS和Glonass信号。