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    ANALOG CAPACITOR ON SUBMICRON PITCH METAL LEVEL
    11.
    发明申请
    ANALOG CAPACITOR ON SUBMICRON PITCH METAL LEVEL 审中-公开

    公开(公告)号：US20190157379A1

    公开(公告)日：2019-05-23

    申请号：US16240194

    申请日：2019-01-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

    IPC: H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L27/108 ,  H01L29/16 ,  H01L27/06 ,  H01L29/66

    Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

    Multi-step deposition of ferroelectric dielectric material
    12.
    发明授权
    Multi-step deposition of ferroelectric dielectric material 有权
    铁电介质材料的多步沉积

    公开(公告)号：US08962350B2

    公开(公告)日：2015-02-24

    申请号：US14169120

    申请日：2014-01-30

    Applicant: Texas Instruments Incorporated

    Inventor： Bhaskar Srinivasan ,  Brian E. Goodlin ,  Haowen Bu ,  Mark Visokay

    IPC: H01L21/00 ,  H01L21/02 ,  C23C18/12 ,  H01L49/02

    CPC classification number: H01L21/02112 ,  C23C16/409 ,  C23C18/1216 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/02263 ,  H01L28/56

    Abstract: Multi-step deposition of lead-zirconium-titanate (PZT) ferroelectric material. An initial portion of the PZT material is deposited by metalorganic chemical vapor deposition (MOCVD) at a low deposition rate, for example at a temperature below about 640 deg C. from vaporized liquid precursors of lead, zirconium, and titanium, and a solvent at a collective flow rate below about 1.1 ml/min, in combination with an oxidizing gas. Following deposition of the PZT material at the low flow rate, the remainder of the PZT film is deposited at a high deposition rate, attained by changing one or more of precursor and solvent flow rate, oxygen concentration in the oxidizing gas, A/B ratio of the precursors, temperature, and the like.

    Abstract translation: 钛酸锆（PZT）铁电材料的多步沉积。 PZT材料的初始部分通过金属有机化学气相沉积（MOCVD）以低沉积速率沉积，例如在低于约640℃的温度下从铅，锆和钛的汽化液体前体和溶剂中沉积 与约1.1ml / min的组合流速与氧化气体组合。 在PZT材料以低流速沉积之后，PZT膜的其余部分以高沉积速率沉积，通过改变前体和溶剂流速，氧化气体中的氧浓度，A / B比 的前体，温度等。

    SEMICONDUCTOR DEVICE WITH NITROGEN DOPED FIELD RELIEF DIELECTRIC LAYER
    13.
    发明申请
    SEMICONDUCTOR DEVICE WITH NITROGEN DOPED FIELD RELIEF DIELECTRIC LAYER 有权

    公开(公告)号：US20250006836A1

    公开(公告)日：2025-01-02

    申请号：US18344769

    申请日：2023-06-29

    Applicant: Texas Instruments Incorporated

    Inventor： Jackson Bauer ,  Yanbiao Pan ,  Bhaskar Srinivasan ,  Pushpa Mahalingam

    IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66

    Abstract: Semiconductor devices including a nitrogen doped field relief dielectric layer are described. The microelectronic device comprises a substrate including a body region having a first conductivity type and a drain drift region having a second conductivity type opposite the first conductivity type; a gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region and a doped field relief dielectric layer on the drift region. Doping of the field relief dielectric layer with nitrogen raises the dielectric constant of the field relief dielectric above that of pure silicon dioxide. Increasing the dielectric constant of the field relief dielectric layer may improve channel hot carrier performance, improve breakdown voltage, and reduce the specific on resistance of the microelectronic device compared to a microelectronic device of similar size with a field relief dielectric which is not doped with nitrogen.

    Methods for etching metal interconnect layers
    16.
    发明授权
    Methods for etching metal interconnect layers 有权

    公开(公告)号：US11605587B2

    公开(公告)日：2023-03-14

    申请号：US16383176

    申请日：2019-04-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Poornika Fernandes ,  Bhaskar Srinivasan ,  Scott William Jessen ,  Guruvayurappan S. Mathur

    IPC: H01L23/522 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

    Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.

    IC having trench-based metal-insulator-metal capacitor
    20.
    发明授权
    IC having trench-based metal-insulator-metal capacitor 有权

    公开(公告)号：US11075157B2

    公开(公告)日：2021-07-27

    申请号：US16564849

    申请日：2019-09-09

    Applicant: Texas Instruments Incorporated

    Inventor： Mona M. Eissa ,  Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Erich Wesley Kinder ,  Bhaskar Srinivasan ,  Brian E. Goodlin

    IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

    Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.

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