公开(公告)号：US12210459B2

公开(公告)日：2025-01-28

申请号：US18303183

申请日：2023-04-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad Wu

IPC: G06F12/10 ,  G06F9/46 ,  G06F9/48 ,  G06F12/08 ,  G06F12/0862 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1027 ,  H03M13/15

Abstract: A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

公开(公告)号：US20240281329A1

公开(公告)日：2024-08-22

申请号：US18654109

申请日：2024-05-03

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/126 ,  H04W24/10 ,  H04W56/00 ,  H04W72/02 ,  H04W72/044 ,  H04W74/08 ,  H04W74/0833

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0685 ,  G06F9/3816 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/126 ,  H04W24/10 ,  H04W56/001 ,  H04W72/02 ,  H04W72/044 ,  H04W74/0841 ,  H04W74/0866 ,  G06F3/0604 ,  G06F2212/608

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

公开(公告)号：US20230254907A1

公开(公告)日：2023-08-10

申请号：US18187027

申请日：2023-03-21

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: H04W74/08 ,  H04W24/10 ,  H04W56/00 ,  H04W72/02 ,  H04W72/044

CPC classification number: H04W74/0841 ,  H04W24/10 ,  H04W56/001 ,  H04W72/02 ,  H04W72/044 ,  H04W74/0866

Abstract: Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.

公开(公告)号：US11663141B2

公开(公告)日：2023-05-30

申请号：US17068721

申请日：2020-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad Wu

IPC: G06F12/10 ,  G06F12/08 ,  G06F9/48 ,  G06F9/46 ,  H03M13/15 ,  G06F12/1027 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/0891 ,  G06F12/0882

CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F9/4881 ,  G06F12/0862 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  H03M13/1575 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

公开(公告)号：US20230013270A1

公开(公告)日：2023-01-19

申请号：US17956136

申请日：2022-09-29

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/126

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

公开(公告)号：US11429527B2

公开(公告)日：2022-08-30

申请号：US16653421

申请日：2019-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad Wu

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0862

Abstract: A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.

公开(公告)号：US11237905B2

公开(公告)日：2022-02-01

申请号：US16874435

申请日：2020-05-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/126

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

公开(公告)号：US20200371877A1

公开(公告)日：2020-11-26

申请号：US16874435

申请日：2020-05-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.