公开(公告)号：US20150061907A1

公开(公告)日：2015-03-05

申请号：US14038350

申请日：2013-09-26

Applicant: Texas Instruments Incorporated

Inventor： Eeshan MIGLANI

IPC: H03M3/00

CPC classification number: H03M3/39 ,  H03M3/30 ,  H03M3/37 ,  H03M3/424 ,  H03M3/464

Abstract: A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog input signal and an output of a digital to analog converter. A comparator receives an output of the loop filter and generates a digital output signal. A reference select logic unit receives the digital output signal as a feedback and generates one or more switching signals. One or more switches are coupled to the comparator and each switch receives a pre-computed reference voltage. The one or more switches are activated by the one or more switching signals in response to the digital output signal.

Abstract translation: 一种用于ΔΣ调制器中的过度环路延迟补偿的技术。 ΔΣ调制器包括环路滤波器。 环路滤波器接收模拟输入信号和数模转换器的输出。 比较器接收环路滤波器的输出并产生数字输出信号。 参考选择逻辑单元接收数字输出信号作为反馈并产生一个或多个切换信号。 一个或多个开关耦合到比较器，并且每个开关接收预先计算的参考电压。 响应于数字输出信号，一个或多个开关被一个或多个开关信号激活。

公开(公告)号：US20220271764A1

公开(公告)日：2022-08-25

申请号：US17182339

申请日：2021-02-23

Applicant: Texas Instruments Incorporated

Inventor： Prasanth K ,  Eeshan MIGLANI ,  Visvesvaraya Appala PENTAKOTA ,  Kartik GOEL ,  Jagannathan VENKATARAMAN ,  Sai Aditya Krishnaswamy NURANI

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/00 ,  H03K5/24

Abstract: A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.

公开(公告)号：US20220200620A1

公开(公告)日：2022-06-23

申请号：US17129180

申请日：2020-12-21

Applicant: Texas Instruments Incorporated

Inventor： Eeshan MIGLANI ,  Visvesvaraya Appala PENTAKOTA ,  Chirag Chandrahas SHETTY

IPC: H03M1/50 ,  H03M1/20 ,  H03M1/46

Abstract: A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.

公开(公告)号：US20210399720A1

公开(公告)日：2021-12-23

申请号：US17463588

申请日：2021-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eeshan MIGLANI ,  Shagun DUSAD

IPC: H03H11/12 ,  G06F1/10 ,  H03K19/20

Abstract: A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter. The filter includes a notch filter and a bandpass filter.

公开(公告)号：US20210152126A1

公开(公告)日：2021-05-20

申请号：US17158449

申请日：2021-01-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahul SHARMA ,  Jagannathan VENKATARAMAN ,  Eeshan MIGLANI ,  Sandeep Kesrimal OSWAL

IPC: H03C1/06 ,  H04B1/04 ,  H03C1/60

Abstract: A system includes a Zero IF transmitter having a mixer and a programmable gain stage. The Zero IF transmitter also includes an intermediate stage between the mixer and the programmable gain stage, wherein the intermediate stage is configured to decouple the mixer and the programmable gain stage.

公开(公告)号：US20210119612A1

公开(公告)日：2021-04-22

申请号：US16943561

申请日：2020-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eeshan MIGLANI ,  Shagun DUSAD

IPC: H03H11/12 ,  H03K19/20 ,  G06F1/10

Abstract: A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter.

公开(公告)号：US20190379391A1

公开(公告)日：2019-12-12

申请号：US16434526

申请日：2019-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eeshan MIGLANI ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M3/00 ,  H04B1/40

Abstract: A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.

公开(公告)号：US20170041019A1

公开(公告)日：2017-02-09

申请号：US15226436

申请日：2016-08-02

Applicant: Texas Instruments Incorporated

Inventor： Eeshan MIGLANI ,  Karthikeyan GUNASEKARAN ,  Santhosh Kumar GOWDHAMAN ,  Shagun DUSAD

IPC: H03M3/00

CPC classification number: H03M3/50 ,  H03M1/00 ,  H03M1/001 ,  H03M1/0626 ,  H03M1/0665 ,  H03M1/12 ,  H03M1/747 ,  H03M3/30 ,  H03M3/34 ,  H03M3/422 ,  H03M3/458 ,  H03M7/3004

Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

Abstract translation: 本公开提供了包括第一输入端口和第二输入端口的Δ-Σ调制器。 这些端口接收差分输入信号。 DAC耦合到第一输入端口和第二输入端口，并且接收差分反馈信号和多个选择信号。 环路滤波器响应差分误差信号产生差分滤波信号。 差分误差信号与差分输入信号和差分反馈信号的差成比例。 量化器响应于差分滤波信号产生量化的输出信号。 耦合在量化器和DAC之间的经修改的DWA块响应于斩波时钟，规则时钟，量化的输出信号和多个选择索引信号产生多个选择信号。 选择索引信号取决于先前生成的多个选择信号。