公开(公告)号：US20210325443A1

公开(公告)日：2021-10-21

申请号：US17362706

申请日：2021-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robert Allan NEIDORFF ,  Henry Litzmann EDWARDS

IPC: G01R31/26 ,  G01R31/30 ,  G01R19/00 ,  G01R19/165 ,  G01R31/50

Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

公开(公告)号：US20170033096A1

公开(公告)日：2017-02-02

申请号：US15292409

申请日：2016-10-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN

IPC: H01L27/02 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66371 ,  H01L29/742

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Abstract translation: 集成电路包括NMOS SCR，其中NMOS晶体管的p型体阱为垂直NPN层堆叠提供基极层。 通过使用在基底区域上具有切口掩模元件的注入掩模注入p型掺杂剂来形成基底层，以便从基底区域阻挡p型掺杂剂。 基极层与集成电路中的逻辑元件中NMOS晶体管的p型体阱同时注入。 随后的退火导致p型掺杂剂扩散到基极区域中，形成具有较低掺杂密度的基极，即在NMOS SCR中的NMOS晶体管的主体阱的相邻区域。 NMOS SCR可以具有对称晶体管，漏极延伸晶体管，或者可以是具有与漏极延伸晶体管集成的对称晶体管的双向NMOS SCR。

公开(公告)号：US20240105840A1

公开(公告)日：2024-03-28

申请号：US18528057

申请日：2023-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L29/0852 ,  H01L29/1033 ,  H01L29/66681

Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

公开(公告)号：US20220352406A1

公开(公告)日：2022-11-03

申请号：US17246068

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahmi HEZAR ,  Henry Litzmann EDWARDS

IPC: H01L31/107 ,  H01L31/02 ,  H01L31/109

Abstract: An integrated circuit includes a photodetector that has an epitaxial layer with a first conductivity type located over a substrate. A buried layer of the first conductivity type is located within the epitaxial layer and has a higher carrier concentration than the epitaxial layer. A semiconductor layer located over the buried layer has an opposite second conductivity type and includes a first sublayer over the buried semiconductor layer and a second sublayer between the first sublayer and the buried layer. The first sublayer has a larger lateral dimension than the second sublayer, and has a lower carrier concentration than the second sublayer.

公开(公告)号：US20220209007A1

公开(公告)日：2022-06-30

申请号：US17136816

申请日：2020-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Boguslaw KOCON ,  Henry Litzmann EDWARDS

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/45

Abstract: A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.

公开(公告)号：US20220199611A1

公开(公告)日：2022-06-23

申请号：US17129495

申请日：2020-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Zaichen CHEN ,  Akram Ali SALMAN ,  Henry Litzmann EDWARDS

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/8249

Abstract: In an example, an electronic device includes a first well having a first conductivity type within a semiconductor substrate and a second well having a second opposite conductivity type within the semiconductor substrate and touching the first well. The device further includes a third well having the first conductivity type within the second well. A metallic structure in direct contact with at least a portion of a surface of the third well thereby forms a Schottky barrier between the third well and the metallic structure.

公开(公告)号：US20200303518A1

公开(公告)日：2020-09-24

申请号：US16897382

申请日：2020-06-10

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Andrew D. STRACHAN

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/40

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

公开(公告)号：US20190148517A1

公开(公告)日：2019-05-16

申请号：US15813934

申请日：2017-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS ,  Andrew D. STRACHAN

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

Abstract: A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

公开(公告)号：US20180175021A1

公开(公告)日：2018-06-21

申请号：US15895694

申请日：2018-02-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua HU

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8222 ,  H01L21/265 ,  H01L21/763 ,  H01L21/762 ,  H01L27/06

CPC classification number: H01L27/0259 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/762 ,  H01L21/76237 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/0623 ,  H01L29/06 ,  H01L29/0692 ,  H01L29/10 ,  H01L29/1095

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US20160163691A1

公开(公告)日：2016-06-09

申请号：US15042233

申请日：2016-02-12

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66371 ,  H01L29/742

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Abstract translation: 集成电路包括NMOS SCR，其中NMOS晶体管的p型体阱为垂直NPN层堆叠提供基极层。 通过使用在基底区域上具有切口掩模元件的注入掩模注入p型掺杂剂来形成基底层，以便从基底区域阻挡p型掺杂剂。 基极层与集成电路中的逻辑元件中NMOS晶体管的p型体阱同时注入。 随后的退火导致p型掺杂剂扩散到基极区域中，形成具有较低掺杂密度的基极，即在NMOS SCR中的NMOS晶体管的主体阱的相邻区域。 NMOS SCR可以具有对称晶体管，漏极延伸晶体管，或者可以是具有与漏极延伸晶体管集成的对称晶体管的双向NMOS SCR。