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11.发明申请公开(公告)号：US20140335811A1
公开(公告)日：2014-11-13
申请号：US13892909
申请日：2013-05-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jayawardan Janardhanan
IPC: H04B1/10
CPC classification number: H04B1/10 , H03H17/0213 , H03H17/0261
Abstract: Undesired variations in a signal are removed by initializing two boundaries comprising an upper boundary and a lower boundary to track the signal level. At least one of the upper boundary and the lower boundary is adjusted encapsulate/track the received signal between the two boundaries when the signal level is outside of the two boundaries. A value computed with reference to at least one of the boundaries is provided as a filter output. As a result, the output comprises desired variations that cross the boundaries and the undesired variations that are within the boundaries are eliminated. In one embodiment, an altimeter sensor signal is filtered such that the undesired variations due to noise and instability of the altimeter are removed and the desired variations representing the change in the altitude are detected and provided without any delay to the navigation subsystem.
Abstract translation: 通过初始化包括上边界和下边界的两个边界来跟踪信号电平来消除信号中不期望的变化。 当信号电平在两个边界之外时，上边界和下边界中的至少一个被调整为封闭/跟踪两个边界之间的接收信号。 参考至少一个边界计算的值被提供为滤波器输出。 结果，输出包括跨越边界的期望变化，并且消除了边界内的不期望的变化。 在一个实施例中，过滤高度计传感器信号，使得由于高度计的噪声和不稳定性而导致的不期望的变化被去除，并且代表高度变化的期望变化被检测并且没有任何延迟地提供给导航子系统。
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公开(公告)号：US20240113722A1
公开(公告)日：2024-04-04
申请号：US18534861
申请日：2023-12-11
Applicant: Texas Instruments Incorporated
Inventor： Jayawardan Janardhanan , Yogesh Darwhekar , Subhashish Mukherjee
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.
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公开(公告)号：US20230013907A1
公开(公告)日：2023-01-19
申请号：US17377698
申请日：2021-07-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish Mukherjee , Jayawardan Janardhanan , Yogesh Darwhekar
Abstract: A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.
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公开(公告)号：US09948312B2
公开(公告)日：2018-04-17
申请号：US15443217
申请日：2017-02-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H03L7/087 , H03L7/0895 , H03L7/1072 , H03L7/113
Abstract: A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase. Upon detection of a terminal condition, the state machine circuit may disable the digital charge pump and enable operation of an analog charge pump.
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公开(公告)号：US09841507B2
公开(公告)日：2017-12-12
申请号：US14665851
申请日：2015-03-23
Applicant: Texas Instruments Incorporated
Inventor： Deric Wayne Waters , Jayawardan Janardhanan
CPC classification number: G01S19/48 , G01S5/0252 , G01S5/0263 , G01S5/14 , G01S19/03 , G01S19/46
Abstract: A wireless device for indoor positioning has a satellite positioning system, a transceiver, a motion measurement system, and a position estimation system. The satellite positioning system is configured to determine a location of the device based on received satellite positioning signals. The wireless local area network transceiver is configured to measure while in the areas of non-reception, signals transmitted by wireless local area network (WLAN) access points (APs). The motion measurement system is configured to measure movement of the wireless device. The position estimation system is configured to determine a reference location, and record measurements of movement. The reference location and the recorded measurements are to be provided to a positioning database that generates a positioning grid.
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Patent Agency Ranking
16.发明授权公开(公告)号：US09667300B2
公开(公告)日：2017-05-30
申请号：US14753940
申请日：2015-06-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H04B1/40 , H03L7/1075 , H03L7/1976
Abstract: A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot.
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17.发明授权公开(公告)号：US09391653B2
公开(公告)日：2016-07-12
申请号：US13892909
申请日：2013-05-13
Applicant: Texas Instruments Incorporated
Inventor： Jayawardan Janardhanan
CPC classification number: H04B1/10 , H03H17/0213 , H03H17/0261
Abstract: Undesired variations in a signal are removed by initializing two boundaries comprising an upper boundary and a lower boundary to track the signal level. At least one of the upper boundary and the lower boundary is adjusted encapsulate/track the received signal between the two boundaries when the signal level is outside of the two boundaries. A value computed with reference to at least one of the boundaries is provided as a filter output. As a result, the output comprises desired variations that cross the boundaries and the undesired variations that are within the boundaries are eliminated. In one embodiment, an altimeter sensor signal is filtered such that the undesired variations due to noise and instability of the altimeter are removed and the desired variations representing the change in the altitude are detected and provided without any delay to the navigation subsystem.
Abstract translation: 通过初始化包括上边界和下边界的两个边界来跟踪信号电平来消除信号中不期望的变化。 当信号电平在两个边界之外时，上边界和下边界中的至少一个被调整为封闭/跟踪两个边界之间的接收信号。 参考至少一个边界计算的值被提供为滤波器输出。 结果，输出包括跨越边界的期望变化，并且消除了边界内的不期望的变化。 在一个实施例中，过滤高度计传感器信号，使得由于高度计的噪声和不稳定性而导致的不期望的变化被去除，并且代表高度变化的期望变化被检测并且没有任何延迟地提供给导航子系统。
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公开(公告)号：US11843392B2
公开(公告)日：2023-12-12
申请号：US17541781
申请日：2021-12-03
Applicant: Texas Instruments Incorporated
Inventor： Jayawardan Janardhanan , Yogesh Darwhekar , Subhashish Mukherjee
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.
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公开(公告)号：US11581897B1
公开(公告)日：2023-02-14
申请号：US17377698
申请日：2021-07-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish Mukherjee , Jayawardan Janardhanan , Yogesh Darwhekar
Abstract: A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.
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公开(公告)号：US10527453B2
公开(公告)日：2020-01-07
申请号：US15845984
申请日：2017-12-18
Applicant: Texas Instruments Incorporated
Inventor： Deric Wayne Waters , Jayawardan Janardhanan , Saket Thukral
IPC: G01C23/00 , G01D18/00 , G01C21/16 , A61B8/00 , A61B8/08 , G01S19/48 , A61B5/00 , G01S19/47 , G01S19/49 , G08B21/04 , G01S19/34 , G06F19/00 , A61B5/053 , H04N5/232 , H04N7/18 , G06F1/32 , G06K9/62 , A61B5/145 , G16H40/40 , G16H20/30 , G16H15/00
Abstract: A system comprises a plurality of sensors, a sensor processor, and a sampling rate engine. The sensor processor is coupled to an output of each sensor of the plurality of sensors. The sensor processor estimates user dynamics in response to a first output signal of a first sensor of the plurality of sensors. The sampling rate engine is coupled to an output of the sensor processor. The sampling rate engine determines a sampling rate value of a second sensor of the plurality of sensors in response to a user dynamics value from the sensor processor. The second sensor comprises a selectable sampling rate. The selectable sampling rate is configured in response to the sampling rate value determined by the sampling rate engine.
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