公开(公告)号：US20190237395A1

公开(公告)日：2019-08-01

申请号：US16378171

申请日：2019-04-08

Applicant: Texas Instruments Incorporated

Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC: H01L23/495 ,  H01L25/16 ,  H01L21/48

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/49544 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49589 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US10312184B2

公开(公告)日：2019-06-04

申请号：US14932055

申请日：2015-11-04

Applicant: Texas Instruments Incorporated

Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US20180076116A1

公开(公告)日：2018-03-15

申请号：US15487186

申请日：2017-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manu J. Prakuzhy ,  Siva P. Gurrum ,  Daryl R. Heussner ,  Stefan W. Wiktor ,  Ken Pham

IPC: H01L23/495 ,  H01L23/31 ,  H02M3/158

CPC classification number: H01L23/49558 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1037 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M3/158

Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.