公开(公告)号：US20220310302A1

公开(公告)日：2022-09-29

申请号：US17215457

申请日：2021-03-29

Applicant: Texas Instruments Incorporated

Inventor： Yi Yan ,  Zhemin Zhang ,  Ken Pham ,  Vijaylaxmi Khanolkar ,  Dongbin Hou

IPC: H01F27/26 ,  H01F27/28 ,  H01F41/02 ,  H01F41/06

Abstract: A microelectronic device includes a magnetic component having a first magnetic core segment and a second magnetic core segment, with a winding lamina between them. The first magnetic core segment includes a winding support portion with ferromagnetic material. The winding lamina is attached to the winding support portion. The first magnetic core segment also includes an extension portion with ferromagnetic material extending from the winding support portion. The winding lamina has winding loops of electrically conductive material that surround ferromagnetic material. A filler material is formed between the winding lamina and the first magnetic core segment, contacting both the winding lamina and the first magnetic core segment. The second magnetic core segment is attached to the extension portion of the first magnetic core segment. The second magnetic core segment includes ferromagnetic material. The winding loops are electrically coupled to external leads through electrical connections.

公开(公告)号：US20230245942A1

公开(公告)日：2023-08-03

申请号：US17589761

申请日：2022-01-31

Applicant: Texas Instruments Incorporated

Inventor： Kwang-Soo Kim ,  Woochan Kim ,  Vivek Arora ,  Ken Pham

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/34 ,  H01L23/49555 ,  H01L24/06 ,  H01L23/3107 ,  H01L21/4803 ,  H01L24/48 ,  H01L2224/06135 ,  H01L2224/48175

Abstract: A described example includes: a heat slug having a board side surface and an opposite top side surface; a package substrate mounted to the heat slug, the package substrate including overhanging leads extending over the board side surface of the heat slug, the package substrate having downset portions including a downset rail that runs along one side of a die mount area; at least one semiconductor device having a backside surface mounted to the board side surface of the heat slug; electrical connections coupling bond pads of the semiconductor device to the overhanging leads of the package substrate and to the downset rail; and mold compound covering the at least one semiconductor device, the electrical connections, a portion of the leads and the board side surface of the heat slug, the top side surface at least partially exposed from the mold compound.

公开(公告)号：US20170125324A1

公开(公告)日：2017-05-04

申请号：US14932055

申请日：2015-11-04

Applicant: Texas Instruments Incorporated

Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC: H01L23/495 ,  H01L25/16 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/49544 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49589 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US10573582B2

公开(公告)日：2020-02-25

申请号：US16378171

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US20190318983A1

公开(公告)日：2019-10-17

申请号：US16455583

申请日：2019-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manu A. Prakuzhy ,  Siva P. Gurrum ,  Daryl R. Heussner ,  Stefan W. Wiktor ,  Ken Pham

IPC: H01L23/495 ,  H02M3/158 ,  H01L23/31

Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

公开(公告)号：US20210013138A1

公开(公告)日：2021-01-14

申请号：US16504816

申请日：2019-07-08

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Ken Pham

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/64 ,  H01L21/48 ,  H01L21/56

Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.

公开(公告)号：US20240194546A1

公开(公告)日：2024-06-13

申请号：US18078923

申请日：2022-12-10

Applicant: Texas Instruments Incorporated

Inventor： Kwang-Soo Kim ,  Vivek Arora ,  Ken Pham

IPC: H01L23/08 ,  H01L23/00 ,  H01L23/492 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/08 ,  H01L23/492 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/32221 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247

Abstract: An electronic device includes a multilevel ceramic body, first, second, and third plates, and first and second semiconductor dies, with the multilevel ceramic body having opposite first and second sides, a first and second openings in the first side, a third opening in the second side, and a ceramic separator structure defining first and second interior portions between the first and second openings. The first plate is attached to the first side and covers the first opening, the second plate is attached to the first side and covers the second opening, the third plate is attached to the second side and covers the third opening, the first semiconductor die is in the first interior portion, and the second semiconductor die is in the second interior portion of the ceramic body.

公开(公告)号：US11430719B2

公开(公告)日：2022-08-30

申请号：US16455583

申请日：2019-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manu A. Prakuzhy ,  Siva P. Gurrum ,  Daryl R. Heussner ,  Stefan W. Wiktor ,  Ken Pham

IPC: H01L23/495 ,  H01L23/31 ,  H02M3/158

Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

公开(公告)号：US11075147B2

公开(公告)日：2021-07-27

申请号：US16504816

申请日：2019-07-08

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Ken Pham

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/64 ,  H01L21/48

Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.

公开(公告)号：US10607927B2

公开(公告)日：2020-03-31

申请号：US15487186

申请日：2017-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manu J. Prakuzhy ,  Siva P. Gurrum ,  Daryl R. Heussner ,  Stefan W. Wiktor ,  Ken Pham

IPC: H01L23/495 ,  H01L23/31 ,  H02M3/158

Abstract: A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.