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    Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips
    11.
    发明申请
    Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips 审中-公开
    嵌入式半导体芯片批量封装低引脚数的结构与方法

    公开(公告)号：US20160005705A1

    公开(公告)日：2016-01-07

    申请号：US14320825

    申请日：2014-07-01

    Applicant: Texas Instruments Incorporated

    Inventor： Mutsumi Masumoto

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/78

    Abstract: A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.

    Abstract translation: 一种以面板格式制造封装半导体器件的方法。 用于一组连续的芯片的平板尺寸包括绝缘板的刚性基板和具有可在高温下可释放的第一粘合剂的表面层的带，芯基膜和具有第二粘合剂的底层 到基底。 将一组固定在第一粘合剂层上，芯片端子具有金属凸块背离第一粘合剂层的端子。 层压低CTE绝缘材料以填充凸块之间的间隙并形成围绕该组的绝缘框架。 研磨层压材料以暴露凸块。 等离子体清洁组件，跨组装溅射均匀的金属层，可选地镀覆金属层，以及图案化金属层以形成重新路由迹线和扩展的接触焊盘。

    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE
    16.
    发明申请
    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE 有权

    公开(公告)号：US20220108955A1

    公开(公告)日：2022-04-07

    申请号：US17517608

    申请日：2021-11-02

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/373

    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE
    17.
    发明申请
    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE 审中-公开

    公开(公告)号：US20200091076A1

    公开(公告)日：2020-03-19

    申请号：US16132906

    申请日：2018-09-17

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/538 ,  H01L23/373 ,  H01L21/56 ,  H01L23/498

    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

    Stress buffer layer in embedded package
    18.
    发明授权
    Stress buffer layer in embedded package 有权

    公开(公告)号：US10580715B2

    公开(公告)日：2020-03-03

    申请号：US16008119

    申请日：2018-06-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

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