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公开(公告)号：US10985763B2
公开(公告)日：2021-04-20
申请号：US16991072
申请日：2020-08-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Qunying Li , Shanmuganand Chellamuthu , Kemal Safak Demirci
Abstract: A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.
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公开(公告)号：US10547267B2
公开(公告)日：2020-01-28
申请号：US15331213
申请日：2016-10-21
Applicant: Texas Instruments Incorporated
Inventor： Qunying Li , Joao Carlos Felicio Brito , Wenxiao Tan
IPC: H02P7/00 , H02P25/034 , H02P7/03
Abstract: Methods and apparatus providing a smooth transition from a pulse width modulation mode to a linear mode to drive a voice coil motor are disclosed. An example apparatus includes an H-bridge; a pulse generator to generate a pulse when the voice coil motor driver transitions from pulse width modulation mode to linear mode; a first boost circuit to, when the pulse is generated, increase a first current being applied to a first gate of a first transistor in the H-bridge, the increase in the first current enabling the first transistor; and a second boost circuit to, when the pulse is generated, provide an additional path to ground from a node coupled to a second gate of a second transistor of the H bridge, the path to ground corresponding to a voltage drop that disables the second transistor.
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公开(公告)号：US10211767B2
公开(公告)日：2019-02-19
申请号：US15396989
申请日：2017-01-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Qunying Li , Juergen Luebbe , Robert E. Whyte, Jr.
Abstract: An integrated circuit includes a motor current input voltage-to-current (VI) converter that receives a motor current sensor voltage from a motor and a reference voltage to generate an output current related to a motor's current. A motor current calibration VI converter compensates for errors in the motor current input VI converter and generates a calibration output current based on the reference voltage, wherein the output current and the calibration output current are combined to form an estimate of the motor's current.
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公开(公告)号：US12072373B2
公开(公告)日：2024-08-27
申请号：US18117516
申请日：2023-03-06
Applicant: Texas Instruments Incorporated
Inventor： Kemal Safak Demirci , Shanmuganand Chellamuthu , Qunying Li
CPC classification number: G01R31/2853 , H03F3/45475 , H03K5/24 , H03K19/20
Abstract: A circuit includes a gain stage, first and second amplifiers, and a comparison circuit. The gain stage has an input and an output. The first amplifier has an input and an output. The input of the first amplifier is coupled to the input of the gain stage. The second amplifier has an input and an output. The input of the second amplifier is coupled to the output of the gain stage. The comparison circuit is coupled to the outputs of the first and second amplifiers. The comparison circuit is configured to compare signals on the outputs of the first and second amplifiers and to generate a fault flag signal responsive to the output signal from the first amplifier being different than the output signal from the second amplifier.
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公开(公告)号：US20180073895A1
公开(公告)日：2018-03-15
申请号：US15263114
申请日：2016-09-12
Applicant: Texas Instruments Incorporated
Abstract: An angular resolver system includes, for example, an imbalance detector for detecting degraded resolver output signals. The imbalance detector includes a first and second power averaging circuits and a comparator circuit. The first power averaging circuit includes a first integrator for generating over a first time window a first average power signal in response to resolver sensor output signals. The second power averaging circuit includes a second integrator for generating over a second time window a second average power signal in response to the resolver sensor output signals, where the first time window is longer than the second time window. The comparator circuit compares the first average power signal and the second average power signal and generates a fault signal when the first average power signal and the second average power signal differ by a selected voltage threshold.
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Patent Agency Ranking
公开(公告)号：US20170117835A1
公开(公告)日：2017-04-27
申请号：US15396989
申请日：2017-01-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Qunying Li , Juergen Luebbe , Robert E. Whyte, JR.
Abstract: An integrated circuit includes a motor current input voltage-to-current (VI) converter that receives a motor current sensor voltage from a motor and a reference voltage to generate an output current related to a motor's current. A motor current calibration VI converter compensates for errors in the motor current input VI converter and generates a calibration output current based on the reference voltage, wherein the output current and the calibration output current are combined to form an estimate of the motor's current.
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公开(公告)号：US09575473B2
公开(公告)日：2017-02-21
申请号：US14821282
申请日：2015-08-07
Applicant: Texas Instruments Incorporated
Inventor： Qunying Li , Juergen Luebbe , Robert E. Whyte, Jr.
Abstract: An integrated circuit includes a motor current input voltage-to-current (VI) converter that receives a motor current sensor voltage from a motor and a reference voltage to generate an output current related to a motor's current. A motor current calibration VI converter compensates for errors in the motor current input VI converter and generates a calibration output current based on the reference voltage, wherein the output current and the calibration output current are combined to form an estimate of the motor's current.
Abstract translation: 集成电路包括电动机电流输入电压 - 电流（VI）转换器，其接收来自电动机的电动机电流传感器电压和参考电压以产生与电动机电流相关的输出电流。 电动机电流校准VI转换器补偿电动机电流输入VI转换器中的误差，并基于参考电压产生校准输出电流，其中输出电流和校准输出电流被组合以形成电动机电流的估计。
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公开(公告)号：US09374064B1
公开(公告)日：2016-06-21
申请号：US14633066
申请日：2015-02-26
Applicant: Texas Instruments Incorporated
Inventor： Qunying Li
Abstract: A series-structure, parallel-structure and combined structure of micro-step resistance network circuits is disclosed. Micro-step resistance is maintained, while the programming switches on-state resistance impact and its VC and TC effect are minimized. The programming switch area size is greatly reduced as compared to conventional systems.
Abstract translation: 公开了微步电阻网络电路的串联结构，并联结构和组合结构。 微步电阻保持不变，编程开关导通电阻冲击，其VC和TC效应最小化。 与常规系统相比，编程开关面积大小大大降低。
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19.发明授权Trim-matched segmented digital-to-analog converter apparatus, systems and methods 有权微调匹配分段数模转换器装置，系统和方法公开(公告)号：US09276598B1
公开(公告)日：2016-03-01
申请号：US14719931
申请日：2015-05-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Qunying Li , Joao Carlos Brito
CPC classification number: H03M1/1057 , H03M1/687 , H03M1/785 , H03M1/808
Abstract: One or more high-order bit linear branches of a segmented DAC are implemented as R-2R networks geometrically down-scaled from the DAC binary portion by a selected factor. The resulting increase in closely-located mismatch is compensated for by implementing a trim circuit at a low-order end of each such linear branch. The trim circuit is designed with a number of trim steps to compensate for the selected linear branch down-scaling factor. Each trim step switches a resistance into the low-order end of the linear branch resulting in an even resistance increment or decrement at the lumped linear branch output. The trim circuit is calibrated to provide an amount of trim at the linear branch output such that the lumped resistance of the trimmed linear branch matches the lumped resistance of the binary portion within a selected tolerance (e.g., generally +/−0.5 LSB).
Abstract translation: 分段DAC的一个或多个高阶位线性分支被实现为从DAC二进制部分几何地缩小了选定因子的R-2R网络。 通过在每个这样的线性分支的低阶端实现微调电路来补偿由紧密定位的失配引起的增加。 微调电路设计有多个修整步骤，以补偿所选择的线性分支下标因子。 每个修整步骤将电阻切换到线性分支的低阶端，导致在集总线性分支输出处的均匀电阻增加或减小。 校准电路被校准以在线性分支输出处提供一定量的微调，使得修整的线性分支的集总电阻在所选公差（例如，一般为+/- 0.5LSB）内匹配二进制部分的集总电阻。
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20.发明授权BEMF monitor gain calibration stage in hard disk drive servo integrated circuit 有权BEMF在硬盘驱动器伺服集成电路中监视增益校准阶段公开(公告)号：US08975964B2
公开(公告)日：2015-03-10
申请号：US13759848
申请日：2013-02-05
Applicant: Texas Instruments Incorporated
Inventor： Qunying Li , Wenxiao Tan , Gregory Swize
CPC classification number: H03G3/00 , H03G1/0088 , H03G3/001
Abstract: A high performance digitalized Programmable Gain Amplifier (PGA). In prior art circuit, a dual-ladder DAC is employed for gain control, the back gate leakage of NMOS resistors in the fine ladder conquers fine ladder nominal current and it produces non-monotonic gain scallop. Two new art design techniques: (1) adaptively control the fine ladder; and (2) use dummy PMOS brunch device leakage compensates for the NMOS resistor device leakage, are proposed so that the non-monotonic scallops are substantially eliminated and 13-bit resolution/accuracy PGA has been achieved.
Abstract translation: 高性能数字化可编程增益放大器（PGA）。 在现有技术的电路中，采用双梯形DAC进行增益控制，精细梯形图中的NMOS电阻的背栅极泄漏征服了细梯级标称电流，并产生非单调增益扇贝。 两种新的艺术设计技巧：（1）适应性地控制细梯; 并且（2）使用虚拟PMOS快速装置漏电补偿NMOS电阻器件泄漏，从而基本上消除了非单调扇贝，并且已经实现了13位分辨率/精度PGA。
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