公开(公告)号：US20170302287A1

公开(公告)日：2017-10-19

申请号：US15485552

申请日：2017-04-12

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US11595053B2

公开(公告)日：2023-02-28

申请号：US17366506

申请日：2021-07-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi Soundararajan ,  Visvesvaraya Pentakota

IPC: H03M1/20

Abstract: An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output.

公开(公告)号：US10903845B2

公开(公告)日：2021-01-26

申请号：US16941718

申请日：2020-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Visvesvaraya Appala Pentakota ,  Rishi Soundararajan ,  Shagun Dusad ,  Chirag Chandrahas Shetty

IPC: H03M1/38 ,  H03K5/24 ,  H03M1/14 ,  H03M1/12 ,  H03M1/00 ,  H03K19/20

Abstract: A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first input signal, a first current terminal, and a second current terminal coupled to the control terminal of the second transistor and the second current terminal of the third transistor; a seventh transistor having a control terminal coupled to the control terminal of the second transistor, a first current terminal coupled to a second voltage supply, and a second current terminal coupled to the first current terminal of the fifth transistor; an eighth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to the second voltage supply, and a second current terminal coupled to the first current terminal of the sixth transistor; a ninth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the second current terminal of the first transistor, and a second current terminal coupled to the second current terminal of the second transistor and the second current terminal of the fifth transistor; and a tenth transistor having a control terminal coupled to the second input signal, a first current terminal coupled to the second terminal of the fourth transistor, and a second current terminal coupled to the second current terminal of the third transistor.

公开(公告)号：US10778243B2

公开(公告)日：2020-09-15

申请号：US16860145

申请日：2020-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Visvesvaraya Appala Pentakota ,  Rishi Soundararajan ,  Shagun Dusad ,  Chirag Chandrahas Shetty

IPC: H03M1/38 ,  H03K5/24 ,  H03M1/00 ,  H03K19/20 ,  H03M1/12 ,  H03M1/14

Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input. The analog-to-digital converter further includes a digital block having an input connected to the sign signal output of the delay comparator.

公开(公告)号：US10673452B1

公开(公告)日：2020-06-02

申请号：US16217643

申请日：2018-12-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi Soundararajan ,  Visvesvaraya Pentakota

IPC: H03M1/20

Abstract: An analog-to-digital converter has first and second comparators and an interpolation comparator. The first comparator receives an input signal and a comparison signal, and generates an output as a function of the input signal and the comparison signal. The second comparator receives the input signal and a second comparison signal (different from the first comparison signal), and generates a second output as a function of the input signal and the second comparison signal. The interpolation comparator, operatively connected to the first and second comparators, receives the first and second outputs, and generates a third output based on relative timing of the first and second outputs.

公开(公告)号：US10320405B2

公开(公告)日：2019-06-11

申请号：US15909378

申请日：2018-03-01

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/10 ,  H03M1/16 ,  H03M1/36

Abstract: In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US09917594B1

公开(公告)日：2018-03-13

申请号：US15466691

申请日：2017-03-22

Applicant: Texas Instruments Incorporated

Inventor： Rishi Soundararajan

IPC: H03M1/00 ,  H03M1/46 ,  H03K5/24 ,  H03M1/06

CPC classification number: H03M1/46 ,  H03K5/2481 ,  H03M1/0607 ,  H03M1/36 ,  H03M1/44 ,  H03M1/48

Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.

公开(公告)号：US20240171190A1

公开(公告)日：2024-05-23

申请号：US18174187

申请日：2023-02-24

Applicant: Texas Instruments Incorporated

Inventor： Sourya Dewan ,  Visvesvaraya Appala Pentakota ,  Rishi Soundararajan ,  Shagan Dusad

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A delay-domain analog-to-digital converter including a voltage-to-delay circuit and a time-to-digital converter circuit, and a method of calibrating the same. The voltage-to-delay circuit generates a delay signal based on applied calibration voltage, and the delay signal is applied to a first residue stage configured to generate a sign bit and a residue delay signal. The residue delay signal is applied to an input of a successive residue stage, which is configured to generate a sign bit and provide a residue delay signal to inputs of a next successive residue stage. First and second trim circuits are provided in a delay comparator of one of the successive residue stages, and configured to adjust a first response of the residue stage for a calibration voltage in a first range, and to adjust a second response of the residue stage for a calibration voltage in a second range.

公开(公告)号：US11316505B2

公开(公告)日：2022-04-26

申请号：US17181073

申请日：2021-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi Soundararajan ,  Visvesvaraya Pentakota

IPC: H03K5/24 ,  H03M1/50 ,  H03K5/00 ,  H03M1/36 ,  H03M1/46 ,  H03M1/48

Abstract: An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.

公开(公告)号：US10673453B1

公开(公告)日：2020-06-02

申请号：US16517796

申请日：2019-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Visvesvaraya Appala Pentakota ,  Rishi Soundararajan ,  Shagun Dusad ,  Chirag Chandrahas Shetty

IPC: H03M1/38 ,  H03K5/24 ,  H03K19/20 ,  H03M1/12 ,  H03M1/00 ,  H03M1/14

Abstract: An analog-to-digital converter has a logic gate for generating an output signal having a delay corresponding to a delay between input signals. The logic gate includes inputs for receiving the input signals, and an output for outputting the output signal. A delay comparator generates a digital signal representative of the order of the input signals, and generates a delay signal having a delay corresponding to the delay between the input signals. The delay comparator has inputs for receiving the input signals, a digital output for outputting the digital signal, and a delay output for outputting the delay signal. A delay-based analog-to-digital converter, with a front stage and successive residual stages, is also disclosed. A delay comparator having merged comparator, sign-out, and delay-out circuits, and which may be operated within one of successive stages, without a clock, is also disclosed.