公开(公告)号：US09985018B2

公开(公告)日：2018-05-29

申请号：US14864504

申请日：2015-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Russell Carlton McMullan ,  Binu Kamblath Pushkarakshan ,  Subramanian J. Narayan ,  Swaminathan Sankaran ,  Keith Edmund Kunz

IPC: H01L49/02 ,  H01L27/06 ,  H01L27/08 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L27/0676 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/24 ,  H01L29/66143 ,  H01L29/8725

Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.

公开(公告)号：US20160071838A1

公开(公告)日：2016-03-10

申请号：US14864504

申请日：2015-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Russell Carlton McMullan ,  Binu Kamblath Pushkarakshan ,  Subramanian J. Narayan ,  Swaminathan Sankaran ,  Keith Edmund Kunz

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/66

CPC classification number: H01L27/0676 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/24 ,  H01L29/66143 ,  H01L29/8725

Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.

公开(公告)号：US09093315B2

公开(公告)日：2015-07-28

申请号：US14099973

申请日：2013-12-08

Applicant: Texas Instruments Incorporated

Inventor： Shaofeng Yu ,  Russell Carlton McMullan ,  Wah Kit Loh

IPC: H01L29/08 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0847

Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

Abstract translation: 包含SAR SRAM和CMOS逻辑的集成电路，其中SAR SRAM单元的栅极延伸上的侧壁间隔物比逻辑PMOS栅极上的侧壁间隔更薄，使得漏极节点SRAM PSD层的深度保持在 伸展接触。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括选择性地蚀刻在SAR SRAM单元的栅极延伸上的侧壁间隔物，使得漏极节点SRAM PSD层的深度保持在拉伸接触下 。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括在漏极节点SRAM PSD层中选择性地注入额外的p型掺杂剂，使得漏极节点SRAM PSD层的深度保持在拉伸接触下。

公开(公告)号：US08962419B2

公开(公告)日：2015-02-24

申请号：US14497697

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan ,  Dong Joo Bae

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823864 ,  H01L21/0217 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7847

Abstract: A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous regions of silicon in the gates of the two transistors, and subsequently removing the stressor layers. A process of forming a CMOS integrated circuit by forming two transistors of opposite polarity, forming a two stressor layers over the transistors, annealing the integrated circuit, removing the stressor layers, and siliciding the transistors. A process of forming a CMOS integrated circuit with an NMOS transistor and a PMOS transistor using a stress memorization technique, by removing the stressor layers with wet etch processes.

Abstract translation: 通过在相反极性的两个MOS晶体管上形成第一应力器层来形成CMOS集成电路的过程，从第一晶体管去除第一应力层的一部分，并在两个晶体管上形成第二应力层。 进行源/漏退火，在两个晶体管的栅极中结晶硅的非晶区域，随后去除应力层。 通过形成具有相反极性的两个晶体管形成CMOS集成电路的过程，在晶体管上形成两个应力层，退火集成电路，去除应力层，以及硅化硅晶体管。 使用应力记忆技术，通过用湿蚀刻工艺去除应力层来形成具有NMOS晶体管和PMOS晶体管的CMOS集成电路的工艺。