公开(公告)号：US09589983B2

公开(公告)日：2017-03-07

申请号：US15172536

申请日：2016-06-03

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan

IPC: H01L27/108 ,  H01L27/12 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/84 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/06 ,  H01L21/74

CPC classification number: H01L27/1203 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/743 ,  H01L21/7624 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/535 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.

Abstract translation: 集成电路在埋入氧化物层中具有将MOS晶体管的主体连接到贯穿衬底通孔（TSV）的掩埋互连。 埋地互连横向延伸穿过TSV。 集成电路通过从衬底开始形成，在衬底的顶表面上形成具有掩埋互连的掩埋氧化物层，并在掩埋氧化物层上形成半导体器件层。 MOS晶体管形成在半导体器件层中，使得主体与掩埋互连件进行电连接。 随后，TSV通过衬底的底表面形成，以便与掩埋氧化物层中的掩埋互连件形成电连接。 晶体管的主体通过掩埋互连电连接到TSV。

公开(公告)号：US20140346609A1

公开(公告)日：2014-11-27

申请号：US14099973

申请日：2013-12-08

Applicant: Texas Instruments Incorporated

Inventor： Shaofeng Yu ,  Russell Carlton McMullan ,  Wah Kit Loh

IPC: H01L27/11 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0847

Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

Abstract translation: 包含SAR SRAM和CMOS逻辑的集成电路，其中SAR SRAM单元的栅极延伸上的侧壁间隔物比逻辑PMOS栅极上的侧壁间隔更薄，使得漏极节点SRAM PSD层的深度保持在 伸展接触。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括选择性地蚀刻在SAR SRAM单元的栅极延伸上的侧壁间隔物，使得漏极节点SRAM PSD层的深度保持在拉伸接触下 。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括在漏极节点SRAM PSD层中选择性地注入额外的p型掺杂剂，使得漏极节点SRAM PSD层的深度保持在拉伸接触下。

公开(公告)号：US10461075B2

公开(公告)日：2019-10-29

申请号：US14864538

申请日：2015-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Russell Carlton McMullan ,  Binu Kamblath Pushkarakshan ,  Subramanian J. Narayan ,  Swaminathan Sankaran ,  Keith Edmund Kunz

IPC: H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L27/08 ,  H01L29/66 ,  H01L29/872

Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.

公开(公告)号：US20160284731A1

公开(公告)日：2016-09-29

申请号：US15172536

申请日：2016-06-03

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/06 ,  H01L23/522 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L21/3205 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L27/1203 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/743 ,  H01L21/7624 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/535 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.

Abstract translation: 集成电路在埋入氧化物层中具有将MOS晶体管的主体连接到贯穿衬底通孔（TSV）的掩埋互连。 埋地互连横向延伸穿过TSV。 集成电路通过从衬底开始形成，在衬底的顶表面上形成具有掩埋互连的掩埋氧化物层，并在掩埋氧化物层上形成半导体器件层。 MOS晶体管形成在半导体器件层中，使得主体与掩埋互连件进行电连接。 随后，TSV通过衬底的底表面形成，以便与掩埋氧化物层中的掩埋互连件形成电连接。 晶体管的主体通过掩埋互连电连接到TSV。

公开(公告)号：US09966373B2

公开(公告)日：2018-05-08

申请号：US15409893

申请日：2017-01-19

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan ,  Kamel Benaissa

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L21/027

CPC classification number: H01L27/088 ,  H01L21/0276 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

公开(公告)号：US20160071839A1

公开(公告)日：2016-03-10

申请号：US14864538

申请日：2015-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Russell Carlton McMullan ,  Binu Kamblath Pushkarakshan ,  Subramanian J. Narayan ,  Swaminathan Sankaran ,  Keith Edmund Kunz

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/872

CPC classification number: H01L27/0676 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/24 ,  H01L29/66143 ,  H01L29/8725

Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.

公开(公告)号：US20170133366A1

公开(公告)日：2017-05-11

申请号：US15409893

申请日：2017-01-19

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan ,  Kamel Benaissa

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L29/45 ,  H01L21/027 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/0276 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

公开(公告)号：US09583609B2

公开(公告)日：2017-02-28

申请号：US13850192

申请日：2013-03-25

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan ,  Kamel Benaissa

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L27/088 ,  H01L21/0276 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

Abstract translation: 形成具有位于第一方向上的纵向轴线的细长金属接触，以形成与延伸的源极和漏极区域的电连接，纵向轴线处于第一方向，并且细长金属与位于第二方向的纵向轴线接触形成 电连接到细长的源极和漏极区域，其中纵向轴线位于第二方向，其中第二方向垂直于第一方向。

公开(公告)号：US09385140B1

公开(公告)日：2016-07-05

申请号：US14614395

申请日：2015-02-04

Applicant: Texas Instruments Incorporated

Inventor： Russell Carlton McMullan

IPC: H01L27/108 ,  H01L27/12 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/84 ,  H01L21/321 ,  H01L21/762

CPC classification number: H01L27/1203 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/743 ,  H01L21/7624 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/535 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.

Abstract translation: 集成电路在埋入氧化物层中具有将MOS晶体管的主体连接到贯穿衬底通孔（TSV）的掩埋互连。 埋地互连横向延伸穿过TSV。 集成电路通过从衬底开始形成，在衬底的顶表面上形成具有掩埋互连的掩埋氧化物层，并在掩埋氧化物层上形成半导体器件层。 MOS晶体管形成在半导体器件层中，使得主体与掩埋互连件进行电连接。 随后，TSV通过衬底的底表面形成，以便与掩埋氧化物层中的掩埋互连件形成电连接。 晶体管的主体通过掩埋互连电连接到TSV。

公开(公告)号：US20140284725A1

公开(公告)日：2014-09-25

申请号：US13850192

申请日：2013-03-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Russell Carlton McMullan ,  Kamel Benaissa

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/0276 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

Abstract translation: 形成具有位于第一方向上的纵向轴线的细长金属接触，以形成与延伸的源极和漏极区域的电连接，纵向轴线处于第一方向，并且细长金属与位于第二方向的纵向轴线接触形成 电连接到细长的源极和漏极区域，其中纵向轴线位于第二方向，其中第二方向垂直于第一方向。