公开(公告)号：US20230393975A1

公开(公告)日：2023-12-07

申请号：US18449025

申请日：2023-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland BEAUDOIN ,  Ritesh Dhirajlal SOJITRA ,  Samuel Paul VISALLI

IPC: G06F12/02 ,  G06F12/0879 ,  G11C29/00 ,  G11C11/409 ,  G11C29/42 ,  G06F13/40

CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F12/0879 ,  G11C29/76 ,  G11C11/409 ,  G11C29/42 ,  G06F13/4027

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

公开(公告)号：US20230326002A1

公开(公告)日：2023-10-12

申请号：US18333151

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY, JR. ,  Veeramanikandan RAJU ,  Niraj NANDAN ,  Samuel Paul VISALLI ,  Jason A.T. JONES ,  Kedar Satish CHITNIS ,  Gregory Raymond SHURTZ ,  Prithvi Shankar YEYYADI ANANTHA ,  Sriramakrishnan GOVINDARAJAN

IPC: G06T7/00 ,  G06T1/20 ,  G06T3/40 ,  G05B23/02

CPC classification number: G06T7/0002 ,  G06T1/20 ,  G06T3/40 ,  H04N17/00 ,  G06T7/97 ,  G06T2207/10016 ,  G05B23/0259

Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.

公开(公告)号：US20230176948A1

公开(公告)日：2023-06-08

申请号：US18102807

申请日：2023-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Samuel Paul VISALLI

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C29/52

Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.