公开(公告)号：US20240195417A1

公开(公告)日：2024-06-13

申请号：US18525464

申请日：2023-11-30

Applicant: Texas Instruments Incorporated

Inventor： Avinash Shah ,  Kashyap Barot ,  Sreeram Nasum S ,  Kumar Anurag Shrivastava ,  Suvadip Banerjee

IPC: H03K19/017 ,  G05B19/05 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/01728 ,  G05B19/054 ,  H03K19/00361 ,  H03K19/00384 ,  H03K19/018557 ,  H03K19/017572

Abstract: An example apparatus includes: a current mirror having first and second outputs; oscillator circuitry including: a first transistor having a first terminal coupled to the first output of the current mirror, having a second terminal, and having a control terminal; and a second transistor having a first terminal coupled to the first output of the current mirror, having a second terminal coupled to the control terminal and the second terminal of the first transistor, and having a control terminal coupled to the second terminals of the first and second transistors; and current shunt circuitry having a terminal coupled to the second output of the current mirror.

公开(公告)号：US11953935B2

公开(公告)日：2024-04-09

申请号：US17867045

申请日：2022-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvadip Banerjee

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/10

Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

公开(公告)号：US20230291305A1

公开(公告)日：2023-09-14

申请号：US17828470

申请日：2022-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anandha Ruban Tiruchengode Tirumurugga Bupathi ,  Suvadip Banerjee ,  Anant Kamath

IPC: H02M1/36 ,  H02M1/32 ,  H02M3/04

CPC classification number: H02M1/36 ,  H02M1/32 ,  H02M3/04

Abstract: Circuits and systems include a parallel resistor-capacitor (RC) network coupled between a pin and ground, and first and second transistors coupled in source follower configuration with a common gate coupling. The source of the first transistor is coupled to the pin. A first switch couples a drain of the first transistor to the common gate coupling during soft-start (SS) and decouples that connection during over current limit (OCL) sensing, and a second switch couples a drain of the second transistor to the common gate coupling during OCL sensing and decouples that connection during SS. A first current source is enabled deliver a constant current to the pin during SS. A second current source is enabled to generate a reference voltage at the source of the second transistor during OCL, which reference voltage is transferred to the pin by the source follower configuration. A comparator controls the switches to transition from SS to OCL sensing. The comparator output signal is based on a comparison of the voltage at the pin to a threshold voltage.

公开(公告)号：US20220246566A1

公开(公告)日：2022-08-04

申请号：US17162189

申请日：2021-01-29

Applicant: Texas Instruments Incorporated

Inventor： Suvadip Banerjee ,  John Paul Tellkamp

IPC: H01L23/00 ,  H01L23/488 ,  H01L23/528 ,  H01L21/48

Abstract: An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

公开(公告)号：US20240235504A9

公开(公告)日：2024-07-11

申请号：US17972518

申请日：2022-10-24

Applicant: Texas Instruments Incorporated

Inventor： Harsh Sheokand ,  Tarunvir Singh ,  Anant Kamath ,  Suvadip Banerjee

IPC: H03F3/45

CPC classification number: H03F3/45654 ,  H03F3/45183 ,  H03F2203/45526

Abstract: A system includes an operational amplifier which includes a first amplifier input, a second amplifier input and an amplifier output. The system includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The system includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The system includes a first bias current source coupled between the first amplifier input and a common potential and includes a second bias current source coupled between the first terminal of the first switch and the common potential. The system includes a feedback path between the amplifier output and the first amplifier input.

公开(公告)号：US20240235422A1

公开(公告)日：2024-07-11

申请号：US18153249

申请日：2023-01-11

Applicant: Texas Instruments Incorporated

Inventor： Anant Kamath ,  Suvadip Banerjee

IPC: H02M7/538 ,  B60L50/51 ,  H02M1/00

CPC classification number: H02M7/538 ,  B60L50/51 ,  H02M1/0064 ,  B60L2210/44

Abstract: In described examples, a converter circuit includes a primary-side ground, a current sensor, a control signal generator, first and second control switches, and a transformer with a center-tapped primary-side coil. A first terminal of the first control switch is coupled to a first terminal of the coil and a first input of the current sensor. A first terminal of the second control switch is coupled to a second terminal of the coil and a second input of the current sensor. Second terminals of the first and second control switches are coupled to ground. The control signal generator closes the first control switch and opens the second control switch in a first phase; opens the first control switch and closes the second control switch in a second phase that alternates with the first phase; and adjusts first phase duration in response to current sensor output, without changing converter period duration.

公开(公告)号：US20230025757A1

公开(公告)日：2023-01-26

申请号：US17489483

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： RR Manikandan ,  Kumar Anurag Shrivastava ,  Robert Floyd Payne ,  Anant Shankar Kamath ,  Swaminathan Sankaran ,  Kishalay Datta ,  Siraj Akhtar ,  Mark Edward Wentroble ,  Suvadip Banerjee ,  Rakesh Hariharan ,  Gurumurti Kailaschandra Avhad

IPC: H04B1/44 ,  H03K3/017 ,  H03K5/24 ,  H04L27/04 ,  H04L27/06

Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

公开(公告)号：US20230023275A1

公开(公告)日：2023-01-26

申请号：US17867045

申请日：2022-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvadip Banerjee

IPC: G06F1/08 ,  G06F1/10

Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

公开(公告)号：US11442490B1

公开(公告)日：2022-09-13

申请号：US17383820

申请日：2021-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvadip Banerjee

IPC: G06F1/06 ,  H03K3/017 ,  H03K19/20 ,  H03K3/037

Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

公开(公告)号：US20220077788A1

公开(公告)日：2022-03-10

申请号：US17236931

申请日：2021-04-21

Applicant: Texas Instruments Incorporated

Inventor： Tarunvir Singh ,  Suvadip Banerjee ,  Sreeram Subramanyam Nasum

IPC: H02M3/335 ,  H02M1/088

Abstract: DC-DC power converter architecture is disclosed. In an example, an integrated circuit includes an H-bridge switching circuit operatively coupled with a transformer. The switching circuit is compensated to account for parasitic differences between the high-side (power) and low-side (ground). For instance, PMOS transistors connected to the high-side are sized larger to substantially match on-resistance of NMOS transistors connected to the low-side (e.g., such that the on-resistances are all within a tolerance of one another, or within a tolerance of a target on-resistance value), and the NMOS transistors include additional gate-drain capacitance to substantially match gate-drain capacitance of the larger PMOS transistors (e.g., such that the gate-drain capacitances are all within a tolerance of one another, or within a tolerance of a target gate-drain capacitance value). In addition, the transformer is configured with physical symmetry, such that the inductive and capacitive mid-points of the transformer are substantially co-located.