公开(公告)号：US20210103469A1

公开(公告)日：2021-04-08

申请号：US17126143

申请日：2020-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton LEYRER ,  William Cronin WALLACE ,  David Alston LIDE

IPC: G06F9/48 ,  G06F16/9035 ,  G06F9/52 ,  G06F9/50 ,  G06F1/06 ,  G06F13/20 ,  G06F9/448 ,  G06F11/10 ,  H04L1/00 ,  G06F13/28 ,  G06F13/40

Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

公开(公告)号：US20190372566A1

公开(公告)日：2019-12-05

申请号：US16424862

申请日：2019-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Anton LEYRER ,  Martin STAEBLER ,  William Cronin WALLACE

IPC: H03K7/08 ,  H03K19/00 ,  G06F11/07

Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.

公开(公告)号：US20180227067A1

公开(公告)日：2018-08-09

申请号：US15891227

申请日：2018-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06

CPC classification number: H04J3/0658 ,  H04J3/0641 ,  H04J3/0667 ,  H04J3/0676 ,  H04J3/0679 ,  H04J3/0688 ,  H04J3/0691 ,  H04L7/0083

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.