公开(公告)号：US11855024B2

公开(公告)日：2023-12-26

申请号：US17463047

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qiao Chen ,  Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Patrick Francis Thompson ,  Jonathan Andrew Montoya ,  Salvatore Frank Pavone

IPC: H01L23/00

CPC classification number: H01L24/09 ,  H01L24/25 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/09181 ,  H01L2224/2541 ,  H01L2224/73209 ,  H01L2224/81801

Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

公开(公告)号：US11854922B2

公开(公告)日：2023-12-26

申请号：US17353805

申请日：2021-06-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Joseph Liu

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L24/02 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/0233 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/221 ,  H01L2224/244 ,  H01L2224/24137 ,  H01L2224/24155 ,  H01L2224/32137 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92135 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104

Abstract: A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

公开(公告)号：US11410947B2

公开(公告)日：2022-08-09

申请号：US16721546

申请日：2019-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

Abstract: A package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer. The package is a wafer chip scale package (WCSP). The package further includes a solder ball attached to the redistribution layer.

公开(公告)号：US20210327829A1

公开(公告)日：2021-10-21

申请号：US16850620

申请日：2020-04-16

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L33/62 ,  H01L23/00 ,  H01L33/00

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.