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    Multiple input signature register analysis for digital circuitry
    11.
    发明授权
    Multiple input signature register analysis for digital circuitry 有权

    公开(公告)号：US11209481B2

    公开(公告)日：2021-12-28

    申请号：US16217289

    申请日：2018-12-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naman Maheshwari ,  Wilson Pradeep ,  Prakash Narayanan

    IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3193 ,  G01R31/3177

    Abstract: A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.

    TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION
    14.
    发明申请
    TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION 审中-公开
    在速度运行模式下对集成电路进行测试

    公开(公告)号：US20150212152A1

    公开(公告)日：2015-07-30

    申请号：US14605354

    申请日：2015-01-26

    Applicant: Texas Instruments Incorporated

    Inventor： Khushboo Agarwal ,  Sanjay Krishna H V ,  Raashid Moin Shaikh ,  Srivaths Ravi ,  Wilson Pradeep ,  Rajesh Kumar Tiwari

    IPC: G01R31/3177

    CPC classification number: G01R31/31721 ,  G01R31/31707 ,  G01R31/31727

    Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

    Abstract translation: 用于测试专用集成电路（ASIC）的方法。 创建一组表示，覆盖用于测试模式功率分析的ASIC的关键子芯片中的一组时钟门的功率密度信息和时钟门物理位置。 基于所述一组表示的重叠，所述表示集合进一步分组成各个组。 然后，在高速测试操作模式期间，对应于该组时钟门限中的每一个产生一组测试控制信号，使得每个具有重叠表示的时钟门接收不同的测试控制信号。 此外，使用虚拟约束函数生成模式以选择性地启用该组测试控制信号，使得该组测试控制信号不被同时激活。

    Testing of integrated circuits during at-speed mode of operation
    16.
    发明授权
    Testing of integrated circuits during at-speed mode of operation 有权

    公开(公告)号：US11333707B2

    公开(公告)日：2022-05-17

    申请号：US16703909

    申请日：2019-12-05

    Applicant: Texas Instruments Incorporated

    Inventor： Khushboo Agarwal ,  Sanjay Krishna Hulical Vijayaraghavachar ,  Raashid Moin Shaikh ,  Srivaths Ravi ,  Wilson Pradeep ,  Rajesh Kumar Tiwari

    IPC: G06F30/33 ,  G01R31/317

    Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

    Multiple input signature register analysis for digital circuitry
    18.
    发明授权
    Multiple input signature register analysis for digital circuitry 有权

    公开(公告)号：US10184980B2

    公开(公告)日：2019-01-22

    申请号：US15395307

    申请日：2016-12-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naman Maheshwari ,  Wilson Pradeep ,  Prakash Narayanan

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3193

    Abstract: A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.

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