公开(公告)号：US12136588B2

公开(公告)日：2024-11-05

申请号：US17379934

申请日：2021-07-19

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/482

Abstract: A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.

公开(公告)号：US11908834B2

公开(公告)日：2024-02-20

申请号：US17741402

申请日：2022-05-10

Applicant: Texas Instruments Incorporated

Inventor： Vivek Arora ,  Woochan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56 ,  H01F27/40 ,  H01F27/06 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01F27/06 ,  H01F27/40 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/4924 ,  H01L23/49503 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/48195 ,  H01L2224/92247

Abstract: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

公开(公告)号：US20230413467A1

公开(公告)日：2023-12-21

申请号：US18459419

申请日：2023-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Vivek Kishorechand Arora ,  David Ryan Huitink ,  Hayden Seth Carlton ,  Fang Luo ,  Asif Imran Emon

IPC: H05K7/14 ,  H05K7/20 ,  H02K7/14 ,  H02M7/00 ,  H05K1/14 ,  H05K1/11

CPC classification number: H05K7/1432 ,  H05K7/209 ,  H02K7/14 ,  H02M7/003 ,  H05K1/144 ,  H05K1/112

Abstract: A power conversion module and method of forming the same includes a motherboard having a first surface and a second surface that opposes the first surface. The motherboard includes a first trace that electrically couples a decoupling capacitor mounted on the motherboard to a first pad on the first surface of the motherboard and an output node of a power conversion module. The motherboard includes a via extending through the motherboard that electrically couples a second pad on the first surface of the motherboard and a third pad on the second surface of the motherboard to the output node and a second trace that electrically couples a fourth pad on the second surface of the motherboard and the decoupling capacitor. The power module includes a first daughterboard mounted on the first surface of the motherboard and a second daughterboard mounted on the second surface of the motherboard.

公开(公告)号：US11715679B2

公开(公告)日：2023-08-01

申请号：US16597808

申请日：2019-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/538 ,  H01L23/495 ,  H01L25/065 ,  H02M3/156 ,  H01L25/07 ,  H01L25/16 ,  H01L21/48 ,  H01L23/48 ,  H02M1/00

CPC classification number: H01L23/49575 ,  H01L21/4885 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5387 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/165 ,  H02M3/156 ,  H02M1/0012

Abstract: A semiconductor package includes a substrate, a set of terminals protruding from a first surface of the substrate, a power stage physically and thermally coupled to the first surface of the substrate, and a flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer. The power stage is between the flexible circuit and the substrate and is mounted on a first surface of the flexible circuit such that the power stage is electrically connected to the power stage conductors. The package includes a die mounted on a second surface of the flexible circuit opposite the power stage. An output of the die is electrically connected to an input of the power stage via the control circuit conductors.

公开(公告)号：US11601065B1

公开(公告)日：2023-03-07

申请号：US17461423

申请日：2021-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Vivek Kishorechand Arora ,  Makoto Shibuya ,  Kengo Aoya

IPC: H02M3/00 ,  H02M7/00 ,  H02M7/527 ,  H01L29/16 ,  H01L29/20 ,  H02M3/158

Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.

公开(公告)号：US20230015323A1

公开(公告)日：2023-01-19

申请号：US17379934

申请日：2021-07-19

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.

公开(公告)号：US20220271008A1

公开(公告)日：2022-08-25

申请号：US17741402

申请日：2022-05-10

Applicant: Texas Instruments Incorporated

Inventor： Vivek Arora ,  Woochan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56 ,  H01F27/40 ,  H01F27/06 ,  H01L25/00

Abstract: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

公开(公告)号：US11417579B2

公开(公告)日：2022-08-16

申请号：US16996742

申请日：2020-08-18

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

公开(公告)号：US11387179B2

公开(公告)日：2022-07-12

申请号：US16827455

申请日：2020-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Kengo Aoya ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/498 ,  H01L23/64 ,  H01L49/02 ,  H01L23/00 ,  H01L21/8234 ,  H01L21/48

Abstract: An integrated circuit (IC) package includes a substrate having a first region and a second region. The substrate includes a conductive path between the first region and the second region. The IC package also includes a lead frame having a first member and a second member that are spaced apart. The IC package further includes a half-bridge power module. The half-bridge power module includes a capacitor having a first node coupled to the first member of the lead frame and a second node coupled to the second member of the lead frame. The half-bridge power module also includes a high side die having a high side field effect transistor (FET) embedded therein and a low side die having a low side FET embedded therein. A source of the high side FET is coupled to a drain of the low side FET through the conductive path of the substrate.

公开(公告)号：US11302615B2

公开(公告)日：2022-04-12

申请号：US16840407

申请日：2020-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.