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    Packaged semiconductor device
    13.
    发明授权
    Packaged semiconductor device 有权

    公开(公告)号：US10475786B1

    公开(公告)日：2019-11-12

    申请号：US16037695

    申请日：2018-07-17

    Applicant: Texas Instruments Incorporated

    Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Makarand Ramkrishna Kulkarni

    IPC: H01L49/02 ,  H03F3/19 ,  H01L27/07 ,  H01L23/31 ,  H05K1/02 ,  H01L23/00 ,  H01L23/522

    Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

    Semiconductor package with electromagnetic interference shielding
    15.
    发明授权
    Semiconductor package with electromagnetic interference shielding 有权

    公开(公告)号：US12165989B2

    公开(公告)日：2024-12-10

    申请号：US18295192

    申请日：2023-04-03

    Applicant: Texas Instruments Incorporated

    Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

    IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498

    Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

    Integrated magnetic assembly
    16.
    发明授权
    Integrated magnetic assembly 有权

    公开(公告)号：US12148556B2

    公开(公告)日：2024-11-19

    申请号：US17383878

    申请日：2021-07-23

    Applicant: Texas Instruments Incorporated

    Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Jonathan Almeria Noquil

    IPC: H01L23/498 ,  H01F17/00 ,  H01F27/28 ,  H01F41/04 ,  H01L21/56 ,  H01L23/495 ,  H01L23/522 ,  H05K1/16

    Abstract: An electronic device includes a multilevel package substrate, conductive leads, a die, and a package structure. The multilevel package substrate has a first level, a second level, and a third level, each having patterned conductive features and molded dielectric features. The first level includes a first patterned conductive feature with multiple turns that form a first winding. The second level includes a second patterned conductive feature, and the third level includes a third patterned conductive feature with multiple turns that form a second winding. A first terminal of the die is coupled to the first end of the first winding, a second terminal of the die is coupled to the second end of the first winding, and a third terminal of the die is coupled to a first conductive lead. The package structure encloses the first die, the second die, and a portion of the multilevel package substrate.

    BACK END OF LINE STRUCTURE FOR IMPROVED CURRENT DENSITY IN HR DEVICES
    20.
    发明公开
    BACK END OF LINE STRUCTURE FOR IMPROVED CURRENT DENSITY IN HR DEVICES 审中-公开

    公开(公告)号：US20240063118A1

    公开(公告)日：2024-02-22

    申请号：US17820020

    申请日：2022-08-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： William Harrison ,  Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Rajen M. Murugan

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/528 ,  H01L24/13 ,  H01L23/5226 ,  H01L21/76885 ,  H01L2224/13025 ,  H01L2224/13147

    Abstract: A semiconductor device is described herein. The semiconductor device generally includes a metal fabrication layer disposed on a substrate. The semiconductor device generally includes a dielectric layer having a first plurality of vias aligned with a first metallization region of the metal fabrication layer and a second plurality of vias aligned with a second metallization region of the metal fabrication layer, the dielectric layer disposed on top of the metal fabrication layer. The semiconductor device generally includes a metal layer disposed on the dielectric layer and having a plurality of metal routings, each of the metal regions disposed over both the first metallization region and the second metallization region, each of the plurality of metal routings have a same width. The semiconductor device generally includes an insulation layer disposed on the metal layer, the insulation layer having a plurality of openings to the metal routings of the metal layer.

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