公开(公告)号：US09136109B2

公开(公告)日：2015-09-15

申请号：US14177939

申请日：2014-02-11

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Yi-Wei Chiu ,  Hsin-Yi Tsai ,  Tzu-Chan Weng ,  Li-Te Hsu

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/0214 ,  H01L21/02329 ,  H01L21/26586 ,  H01L21/28247 ,  H01L21/823814 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.

Abstract translation: 半导体器件包括硅基衬底，栅极结构和层叠的牺牲氧化物层。 栅极结构在硅基衬底上。 层叠的牺牲氧化物层具有硅基衬底上的第一部分和与栅极结构共形的第二部分，其中第一部分的第一厚度基本上与第二部分的第二厚度相同。 层叠的牺牲氧化物层包括自然氧化物层和氮氧化硅层。 天然氧化物层位于硅基衬底上，并与门结构保持一致。 氮氧化硅层与天然氧化物层共形。

公开(公告)号：US12300741B2

公开(公告)日：2025-05-13

申请号：US18178660

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chia-Cheng Tai ,  Tzu-Chan Weng ,  Yi-Wei Chiu ,  Chih Hsuan Cheng

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

公开(公告)号：US10510875B2

公开(公告)日：2019-12-17

申请号：US16000689

申请日：2018-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

公开(公告)号：US20190035908A1

公开(公告)日：2019-01-31

申请号：US16000689

申请日：2018-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/306 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

公开(公告)号：US20240371650A1

公开(公告)日：2024-11-07

申请号：US18775605

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US20230142157A1

公开(公告)日：2023-05-11

申请号：US18149267

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/324 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/41791 ,  H01L29/0847 ,  H01L21/30625 ,  H01L27/092 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/66545 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/845

Abstract: A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.

公开(公告)号：US11545562B2

公开(公告)日：2023-01-03

申请号：US16715347

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/70 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/84

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

公开(公告)号：US11532481B2

公开(公告)日：2022-12-20

申请号：US16916465

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01J37/32

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US11522050B2

公开(公告)日：2022-12-06

申请号：US17104938

申请日：2020-11-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jui Fu Hsieh ,  Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Jen Chen ,  Tzu-Chan Weng

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma etching process comprises applying pulsed bias voltage and RF voltage with pulsed power.

公开(公告)号：US20220367196A1

公开(公告)日：2022-11-17

申请号：US17814607

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01J37/32

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.