公开(公告)号：US20250107176A1

公开(公告)日：2025-03-27

申请号：US18475782

申请日：2023-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Jui-Chien Huang ,  Szuya Liao

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A complementary field-effect transistor (CFET) device includes: a fin; first channel regions disposed vertically over the fin; second channel regions disposed vertically over the first channel regions; an isolation structure between the first and the second channel regions; a first etch stop layer (ESL) on a lower surface of the isolation structure; a second ESL on an upper surface of the isolation structure, where the first ESL, the second ESL, the first channel regions, and the second channel regions are a same semiconductor material; first source/drain regions at opposing ends of the first channel regions; second source/drain regions at opposing ends of the second channel regions; dielectric structures at opposing ends of the isolation structure and disposed vertically between the first and the second source/drain regions; a first gate structure around the first channel regions; and a second gate structure around the second channel regions.

公开(公告)号：US20240250142A1

公开(公告)日：2024-07-25

申请号：US18623285

申请日：2024-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Yi-Bo Liao ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

公开(公告)号：US11699742B2

公开(公告)日：2023-07-11

申请号：US17199877

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/7851

Abstract: A method includes providing a structure having a frontside and a backside, the structure including a substrate, two or more semiconductor channel layers over the substrate and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure; recessing the first S/D feature, thereby exposing a terminal end of one of the semiconductor channel layers; and depositing a dielectric layer on the first S/D feature and covering the exposed terminal end of the one of the semiconductor channel layers.

公开(公告)号：US11699733B2

公开(公告)日：2023-07-11

申请号：US17397099

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.

公开(公告)号：US11532720B2

公开(公告)日：2022-12-20

申请号：US16996094

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Hou-Yu Chen ,  Ching-Wei Tsai

IPC: H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor layer, a gate structure, a source/drain epitaxial structure, a backside dielectric cap, and an inner spacer. The gate structure wraps around the semiconductor layer. The source/drain epitaxial structure is adjacent the gate structure and electrically connected to the semiconductor layer. The backside dielectric cap is disposed under and in direct contact with the gate structure. The inner spacer is in direct contact with the gate structure and the backside dielectric cap.

公开(公告)号：US11532715B2

公开(公告)日：2022-12-20

申请号：US17397596

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yi-Bo Liao ,  Cheng-Ting Chung ,  Yu-Xuan Huang ,  Kuan-Lun Cheng

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.

公开(公告)号：US20220336461A1

公开(公告)日：2022-10-20

申请号：US17859638

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

Abstract: A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

公开(公告)号：US20220199523A1

公开(公告)日：2022-06-23

申请号：US17693925

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Cheng-Ting Chung ,  Wei Ju Lee

IPC: H01L23/522 ,  H01L21/768

Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.

公开(公告)号：US20220165885A1

公开(公告)日：2022-05-26

申请号：US17671156

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

公开(公告)号：US11282935B2

公开(公告)日：2022-03-22

申请号：US16583485

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Yi-Bo Liao ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/321 ,  H01L21/311 ,  H01L29/08 ,  H01L29/40

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.