公开(公告)号：US10186492B1

公开(公告)日：2019-01-22

申请号：US15652249

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Nan-Chin Chuang

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/60 ,  H01L21/56 ,  H01L21/683 ,  H01Q1/22 ,  H01L21/66

Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.

公开(公告)号：US10157807B2

公开(公告)日：2018-12-18

申请号：US15235106

申请日：2016-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC: H01L23/31 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/66 ,  H01L23/00 ,  H01Q9/04 ,  H01L21/56

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

公开(公告)号：US11705409B2

公开(公告)日：2023-07-18

申请号：US16916066

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chao-Wen Shih ,  Han-Ping Pu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/66 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/5226 ,  H01L2223/6677

Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

公开(公告)号：US20200258799A1

公开(公告)日：2020-08-13

申请号：US16858743

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC: H01L23/31 ,  H01Q1/22 ,  H01Q21/06 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/66 ,  H01L23/00 ,  H01Q9/04

Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.

公开(公告)号：US20190355694A1

公开(公告)日：2019-11-21

申请号：US16524146

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/66 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US20190333877A1

公开(公告)日：2019-10-31

申请号：US15965995

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chao-Wen Shih ,  Han-Ping Pu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu

IPC: H01L23/66 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device including a chip package, a dielectric structure and a first antenna pattern is provided. The dielectric structure disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. A manufacturing method of a semiconductor device is also provided.

公开(公告)号：US20190157224A1

公开(公告)日：2019-05-23

申请号：US16252728

申请日：2019-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Nan-Chin Chuang

IPC: H01L23/66 ,  H01Q1/22 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/60 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/66 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/32 ,  H01L23/3135 ,  H01L23/315 ,  H01L23/481 ,  H01L23/60 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01Q1/2283 ,  H01Q1/40 ,  H01Q9/30

Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.

公开(公告)号：US20190115271A1

公开(公告)日：2019-04-18

申请号：US16219979

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC: H01L23/31 ,  H01Q21/06 ,  H01Q9/04 ,  H01Q1/22 ,  H01L21/768 ,  H01L23/00 ,  H01L23/66 ,  H01L23/528 ,  H01L23/48

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

公开(公告)号：US20190067220A1

公开(公告)日：2019-02-28

申请号：US15690287

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/48

Abstract: A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.

公开(公告)号：US10978782B2

公开(公告)日：2021-04-13

申请号：US16858743

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC: H01L23/31 ,  H01Q1/38 ,  H01L23/66 ,  H01Q1/22 ,  H01Q21/06 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01Q9/04 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.