公开(公告)号：US20220359675A1

公开(公告)日：2022-11-10

申请号：US17872160

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

Abstract: A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.

公开(公告)号：US20220140142A1

公开(公告)日：2022-05-05

申请号：US17576725

申请日：2022-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L29/417 ,  H01L21/762 ,  H01L21/764

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US11322394B2

公开(公告)日：2022-05-03

申请号：US16751136

申请日：2020-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Wang-Jung Hsueh ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L21/768 ,  H01L29/423 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/417 ,  H01L29/08 ,  H01L29/49

Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

公开(公告)号：US11271112B2

公开(公告)日：2022-03-08

申请号：US16663085

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Kuo-Yi Chao ,  Rueijer Lin ,  Chen-Yuan Kao ,  Mei-Yun Wang

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L29/45

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure over a substrate and forming a gate dielectric layer over the fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer and forming a source/drain (S/D) structure adjacent to the gate electrode layer. In addition, the method includes forming an S/D contact structure over the S/D structure. The method also includes forming a first conductive layer in direct with the gate electrode layer. A bottom surface of the first conductive layer is lower than a top surface of the gate dielectric layer. The method further includes forming a second conductive layer over the first conductive layer. The gate electrode layer is electrically connected to the second conductive layer by the first conductive layer.

公开(公告)号：US11189525B2

公开(公告)日：2021-11-30

申请号：US16797375

申请日：2020-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Mei-Yun Wang ,  Kuo-Yi Chao ,  Wang-Jung Hsueh

IPC: H01L21/768 ,  H01L27/11 ,  H01L23/522 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

公开(公告)号：US11177212B2

公开(公告)日：2021-11-16

申请号：US16846910

申请日：2020-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/528

Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.

公开(公告)号：US20210098376A1

公开(公告)日：2021-04-01

申请号：US16984884

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC: H01L23/535 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US20190259657A1

公开(公告)日：2019-08-22

申请号：US16403921

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

IPC: H01L21/768 ,  H01L23/485 ,  H01L29/08 ,  H01L29/40 ,  H01L21/311 ,  H01L29/43 ,  H01L21/8234

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

公开(公告)号：US12243940B2

公开(公告)日：2025-03-04

申请号：US18336561

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/764 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US20240290654A1

公开(公告)日：2024-08-29

申请号：US18655763

申请日：2024-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pang-Sheng Chang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Li-Chieh Wu ,  Chun-Wei Hsu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/76814 ,  H01L23/5226 ,  H01L23/53266

Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.