公开(公告)号：US20200335499A1

公开(公告)日：2020-10-22

申请号：US16919063

申请日：2020-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

公开(公告)号：US10811538B2

公开(公告)日：2020-10-20

申请号：US16678637

申请日：2019-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The gate stack has a work function layer and a gate dielectric layer, and tops of the work function layer and the gate dielectric layer are at different height levels. The semiconductor device also includes a protection element over the gate stack. The semiconductor device further includes a spacer extending along a side surface of the protection element and a sidewall of the gate stack.

公开(公告)号：US20200328308A1

公开(公告)日：2020-10-15

申请号：US16915500

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Kai-Yu Cheng ,  Chih-Han Lin ,  Sin-Yi Yang ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.

公开(公告)号：US20200295192A1

公开(公告)日：2020-09-17

申请号：US16886792

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US10727178B2

公开(公告)日：2020-07-28

申请号：US15964276

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/288 ,  H01L23/532 ,  H01L21/027 ,  H01L21/321 ,  H01L29/06

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

公开(公告)号：US10714581B2

公开(公告)日：2020-07-14

申请号：US15901343

申请日：2018-02-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/417 ,  H01L27/108

Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.

公开(公告)号：US20200118923A1

公开(公告)日：2020-04-16

申请号：US16713862

申请日：2019-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/027 ,  H01L21/288 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L23/528

Abstract: A method includes providing a substrate, wherein the substrate includes a conductive feature in a top portion of the substrate; forming a buffer layer over the substrate; forming a dielectric layer over the buffer layer; performing a first etching process to form an opening in the dielectric layer, thereby exposing a top surface of the buffer layer; and performing a second etching process to extend the opening downwardly into the buffer layer, thereby exposing a top surface of the conductive feature, wherein the performing of the second etching process includes laterally enlarging a footing profile of the opening.

公开(公告)号：US10529822B2

公开(公告)日：2020-01-07

申请号：US15650387

申请日：2017-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Li Cheng ,  Che-Cheng Chang

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/165

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. In addition, a sidewall of the gate structure has a top portion having a first inclination, a middle portion having a second inclination, and a bottom portion having a third inclination, and the first inclination, the second inclination, and the third inclination are different from one another.

公开(公告)号：US10510897B2

公开(公告)日：2019-12-17

申请号：US16226875

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.

公开(公告)号：US10355135B2

公开(公告)日：2019-07-16

申请号：US15788803

申请日：2017-10-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Tung-Wen Cheng ,  Chang-Yin Chen ,  Mu-Tsang Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/3213

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.