公开(公告)号：US20210023678A1

公开(公告)日：2021-01-28

申请号：US17068375

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Hao-Yun Cheng ,  Che-Hao Tu ,  Kei-Wei Chen

IPC: B24B57/02 ,  B24B37/10 ,  H01L21/306 ,  B24B37/04 ,  B24B37/30

Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.

公开(公告)号：US20200094369A1

公开(公告)日：2020-03-26

申请号：US16538464

申请日：2019-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu

IPC: B24B37/005 ,  B24B51/00 ,  H01L21/67

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

公开(公告)号：US20190287852A1

公开(公告)日：2019-09-19

申请号：US15922682

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  KEI-WEI CHEN ,  Chih-Wen Liu ,  You-Shiang Lin ,  Yi-Ching Liang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L23/532 ,  H01L21/3213

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

公开(公告)号：US09711374B2

公开(公告)日：2017-07-18

申请号：US13916827

申请日：2013-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  Chih-Yu Chang ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L21/321 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/3212 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/32105 ,  H01L29/66545

Abstract: Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation.

公开(公告)号：US20150187594A1

公开(公告)日：2015-07-02

申请号：US14141028

申请日：2013-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/31055 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66545

Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底上形成伪栅极，在虚拟栅极上沉积第一介电层，化学机械抛光以将第一介电层退回到虚拟栅极的高度，蚀刻以使第一电介质 在栅极的高度以下，在第一介电层上沉积一个或多个附加电介质层，以及化学机械抛光以将一个或多个另外的介电层退回到栅极的高度。 该方法提供了集成电路器件，其具有金属栅极电极和栅极电平处的包括封盖层的级间电介质。 封盖层抵抗蚀刻并通过替换浇口工艺保持浇口高度。