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    Composite structure for gate level inter-layer dielectric
    3.
    发明授权
    Composite structure for gate level inter-layer dielectric 有权
    门级层间电介质复合结构

    公开(公告)号：US09595450B2

    公开(公告)日：2017-03-14

    申请号：US14141028

    申请日：2013-12-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

    IPC: H01L27/088 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8234

    CPC classification number: H01L21/31055 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66545

    Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.

    Abstract translation: 形成集成电路器件的方法包括在半导体衬底上形成伪栅极，在虚拟栅极上沉积第一介电层，化学机械抛光以将第一介电层退回到虚拟栅极的高度，蚀刻以使第一电介质 在栅极的高度以下，在第一介电层上沉积一个或多个附加电介质层，以及化学机械抛光以将一个或多个另外的介电层退回到栅极的高度。 该方法提供了集成电路器件，其具有金属栅极电极和栅极电平处的包括封盖层的级间电介质。 封盖层抵抗蚀刻并通过替换浇口工艺保持浇口高度。

    Hard Mask Removal Method
    5.
    发明申请
    Hard Mask Removal Method 有权

    公开(公告)号：US20210225657A1

    公开(公告)日：2021-07-22

    申请号：US17220595

    申请日：2021-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

    IPC: H01L21/3105 ,  H01L21/306 ,  H01L21/8234

    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

    Planarization control in semiconductor manufacturing process
    6.
    发明授权
    Planarization control in semiconductor manufacturing process 有权

    公开(公告)号：US10541139B2

    公开(公告)日：2020-01-21

    申请号：US15079243

    申请日：2016-03-24

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

    IPC: H01L21/28 ,  H01L29/66 ,  H01L21/321 ,  H01L21/3105

    Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.

    Planarization Control in Semiconductor Manufacturing Process
    7.
    发明申请
    Planarization Control in Semiconductor Manufacturing Process 审中-公开

    公开(公告)号：US20170278712A1

    公开(公告)日：2017-09-28

    申请号：US15079243

    申请日：2016-03-24

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

    Inventor： Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

    IPC: H01L21/28 ,  H01L29/66

    Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.

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