公开(公告)号：US11450555B2

公开(公告)日：2022-09-20

申请号：US17200198

申请日：2021-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

Abstract: A method includes forming a first trench in a semiconductor substrate. A mask is filled in the first trench and over the semiconductor substrate. After filling the mask in the first trench, the mask is patterned to form an opening in the mask. A second trench is formed in the semiconductor substrate. A depth of the second trench is different from a depth of the first trench. After forming the second trench in the semiconductor substrate, the mask is removed. A dielectric material is filled in both the first and second trenches.

公开(公告)号：US11063117B2

公开(公告)日：2021-07-13

申请号：US15492472

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Yong-En Syu ,  Kuo-Hwa Tzeng ,  Ke-Dian Wu ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ming-Che Yang ,  Wei-Kung Tsai

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/15

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a supporting substrate. The semiconductor device structure also includes a first carrier-trapping layer covering the supporting substrate. The first carrier-trapping layer is doped with a group-IV dopant. The semiconductor device structure further includes an insulating layer covering the first carrier-trapping layer. In addition, the semiconductor device structure includes a semiconductor substrate over the insulating layer. The semiconductor device structure also includes a transistor. The transistor includes a gate stack over the semiconductor substrate and source and drain structures in the semiconductor substrate.

公开(公告)号：US10950490B2

公开(公告)日：2021-03-16

申请号：US16222769

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L27/105 ,  H01L27/146

Abstract: A semiconductor structure includes a semiconductor substrate, a first fin, a second fin, a first isolation structure, and a second isolation structure. The semiconductor substrate has a memory device region and a logic core region. The first fin is in the memory device region of the semiconductor substrate. The second fin is in the logic core region of the semiconductor substrate. The first isolation structure is around the first fin. The second isolation structure is around the second fin, and a thickness of the first isolation structure is different from a thickness of the second isolation structure.

公开(公告)号：US20210074551A1

公开(公告)日：2021-03-11

申请号：US16567290

申请日：2019-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC: H01L21/322 ,  H01L23/66 ,  H01L29/06 ,  H01L29/34 ,  H01L21/762

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

公开(公告)号：US10923503B2

公开(公告)日：2021-02-16

申请号：US16024962

申请日：2018-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Min-Ying Tsai ,  Alex Usenko

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/331 ,  H01L21/76 ,  H01L21/70 ,  H01L27/12 ,  H01L21/02 ,  H01L29/16 ,  H01L21/762 ,  H01L21/84 ,  H01L29/04 ,  H01L29/20 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L31/09

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).

公开(公告)号：US10818558B2

公开(公告)日：2020-10-27

申请号：US14738527

申请日：2015-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Cheng Chou ,  Shiu-Ko Jangjian ,  Cheng-Ta Wu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L21/324 ,  H01L27/088

Abstract: A method for manufacturing a semiconductor structure is provided. A plurality of trenches are formed in a substrate. The trenches define at least one fin therebetween. The fin is hydrogen annealed. A dielectric material is formed in the trenches. The dielectric material in the trenches is recessed.

公开(公告)号：US10658474B2

公开(公告)日：2020-05-19

申请号：US16103101

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US10553474B1

公开(公告)日：2020-02-04

申请号：US16139357

申请日：2018-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuan-Liang Liu ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L21/762 ,  H01L21/3213

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

公开(公告)号：US20190259655A1

公开(公告)日：2019-08-22

申请号：US16405165

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16

Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.

公开(公告)号：US10192985B2

公开(公告)日：2019-01-29

申请号：US14805450

申请日：2015-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Ting-Chun Wang ,  Wei-Ming You ,  J. W. Wu

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324

Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.