公开(公告)号：US20160204245A1

公开(公告)日：2016-07-14

申请号：US14677405

申请日：2015-04-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Chih-Nan WU ,  Chun-Che LIN ,  Ting-Chun WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

Abstract translation: 提供了一种翅片场设备结构及其形成方法。 FinFET器件结构包括从衬底延伸的衬底和鳍结构。 FinFET器件结构还包括形成在衬底上的隔离结构。 翅片结构具有顶部和底部，并且底部嵌入隔离结构中。 FinFET器件结构还包括形成在鳍结构的顶部上的保护层。 界面处于保护层和翅片结构的顶部之间，并且界面的粗糙度在约0.1nm至约2.0nm的范围内。

公开(公告)号：US20150364580A1

公开(公告)日：2015-12-17

申请号：US14483935

申请日：2014-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko JANGJIAN ,  Tzu-Kai LIN ,  Chi-Cherng JENG

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/785

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of germanium greater than that of the epitaxially grown source/drain structure.

Abstract translation: 提供了半导体器件的结构和形成方法。 半导体器件包括在半导体衬底上的半导体衬底和鳍状结构。 半导体器件还包括覆盖翅片结构的一部分的栅极堆叠以及在鳍结构上并且邻近栅堆叠的外延生长的源极/漏极结构。 半导体器件还包括在外延生长的源极/漏极结构上的半导体保护层。 半导体保护层的锗原子浓度大于外延生长的源极/漏极结构的原子浓度。

公开(公告)号：US20150179690A1

公开(公告)日：2015-06-25

申请号：US14135042

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Volume CHIEN ,  Fu-Cheng CHANG ,  Yi-Hsing CHU ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG

IPC: H01L27/146 ,  H01L27/148

CPC classification number: H01L27/1463 ,  H01L27/1464

Abstract: Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate. The image sensor device also includes an active region in the semiconductor substrate and surrounded by the isolation structure. The active region includes a light sensing region and a doped region, and the doped region has a horizontal length and a vertical length. A ratio of the horizontal length to the vertical length is in a range from about 1 to about 4.

Abstract translation: 提供了用于形成图像传感器装置的机构的实施例。 图像传感器装置包括半导体衬底和半导体衬底中的隔离结构。 图像传感器装置还包括半导体衬底中的有源区并被隔离结构包围。 有源区包括光感测区和掺杂区，掺杂区具有水平长度和垂直长度。 水平长度与垂直长度的比率在约1至约4的范围内。

公开(公告)号：US20150171136A1

公开(公告)日：2015-06-18

申请号：US14105063

申请日：2013-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Volume CHIEN ,  Zen-Fong HUANG ,  Chia-Yu WEI ,  Chi-Cherng JENG ,  Hsin-Chi CHEN

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14689

Abstract: A backside illuminated CMOS image sensor and a manufacturing method thereof are provided. Embedded micro-lenses disposed respectively on concave surfaces of a buffer oxide layer, wherein the concave surfaces are positioned to respectively align with photodiodes of pixel array of the CMOS image sensor. The embedded micro-lenses can confine incident light to the photodiodes to reduce optical crosstalk between adjacent pixels.

Abstract translation: 提供背面照明CMOS图像传感器及其制造方法。 分别设置在缓冲氧化物层的凹面上的嵌入式微透镜，其中凹面被分别对准与CMOS图像传感器的像素阵列的光电二极管对准。 嵌入式微透镜可以将入射光限制在光电二极管上，以减少相邻像素之间的光学串扰。

公开(公告)号：US20240021651A1

公开(公告)日：2024-01-18

申请号：US18360605

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Volume CHIEN ,  Su-Hua CHANG ,  Chia-Yu WEI ,  Zen-Fong HUANG ,  Chi-Cherng JENG

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14627 ,  H01L27/14623 ,  H01L27/14632 ,  H01L27/14687 ,  H01L31/02164

Abstract: An image sensor includes a pixel array, a dielectric layer, a plurality of first conductive shielding regions, and a plurality of second conductive shielding regions. The pixel array includes photodiodes within a substrate. The dielectric layer is over the substrate. From a plan view, the first conductive shielding regions are adjacent four corners of the pixel array, and the second conductive shielding regions are adjacent four sides of the pixel array. The second conductive region has a length-to-width ratio greater than a length-to-width ratio of the first conductive region.

公开(公告)号：US20230253262A9

公开(公告)日：2023-08-10

申请号：US17813000

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko JANGJIAN ,  Tzu-Kai LIN ,  Chi-Cherng JENG

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/02 ,  H01L21/324 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L29/785 ,  H01L29/66795 ,  H01L21/823814 ,  H01L27/0924 ,  H01L21/02532 ,  H01L21/324 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

公开(公告)号：US20190252547A1

公开(公告)日：2019-08-15

申请号：US16396852

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Barn CHEN ,  Ting-Huang KUO ,  Shiu-Ko JANGJIAN ,  Chi-Cherng JENG

IPC: H01L29/78 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/7851 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/66795

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure over a substrate, and a second fin structure over the substrate. The FinFET device structure also includes a first isolation structure over the substrate and surrounding the first fin structure. The first fin structure is protruded from a top surface of the first isolation structure. The FinFET device structure further includes a second isolation structure over the substrate and surrounding the second fin structure. The second fin structure is protruded from a top surface of the second isolation structure, and the first fin structure has a vertical sidewall surface and the second fin structure has a sloped sidewall surface.

公开(公告)号：US20190139895A1

公开(公告)日：2019-05-09

申请号：US15884760

申请日：2018-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cherng JENG ,  Shyh-Wei CHENG ,  Yun CHANG ,  Chen-Chieh CHIANG ,  Jung-Chi JENG

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a trench. The trench has an inner wall and a bottom surface. The method includes forming a second mask layer in the trench. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method includes removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.

公开(公告)号：US20180277582A1

公开(公告)日：2018-09-27

申请号：US15985351

申请日：2018-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yun-Wei CHENG ,  Chun-Hao CHOU ,  Yin-Chieh HUANG ,  Wan-Chen HUANG ,  Zhe-Ju LIU ,  Kuo-Cheng LEE ,  Chi-Cherng JENG

IPC: H01L27/146

Abstract: An image sensor includes a substrate, a photosensitive unit, a first grid and a color filter. The photosensitive unit is located within the substrate. The first grid is located above the substrate, and the first grid has a first portion and a second portion above the first portion, wherein the second portion has a rounded top surface extending from a sidewall of the first portion of the first grid. The color filter is located above the photosensitive unit and in contact with the rounded top surface of the second portion of the first grid.

公开(公告)号：US20180076091A1

公开(公告)日：2018-03-15

申请号：US15813448

申请日：2017-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko JANGJIAN ,  Ren-Hau Yu ,  Chi-Cherng JENG

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4966

Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.