公开(公告)号：US20190221276A1

公开(公告)日：2019-07-18

申请号：US16159214

申请日：2018-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Der CHIH ,  Chien-Yin LIU ,  Yi-Chun SHIH

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/10 ,  G11C16/26

Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.

公开(公告)号：US20170329669A1

公开(公告)日：2017-11-16

申请号：US15153358

申请日：2016-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Yin LIU ,  Hsueh-Chih YANG ,  Kuan-Chun CHEN ,  Yue-Der CHIH ,  Yi-Chun SHIH

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0411

Abstract: The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to detect a location one to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream.

公开(公告)号：US20160372169A1

公开(公告)日：2016-12-22

申请号：US15250212

申请日：2016-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yue-Der CHIH ,  Cheng-Hsiung KUO ,  Gu-Huan LI ,  Chien-Yin LIU

IPC: G11C7/20 ,  G11C5/02

CPC classification number: G11C7/20 ,  G11C5/02 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/406 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.

Abstract translation: 公开了一种用于具有刷新操作的存储器单元编程和擦除的方法和系统。 该系统包括选择模块，处理模块和刷新模块。 在该方法中，首先，选择来自存储装置中的多个存储单元的目标存储单元。 此后，通过对目标存储单元施加选择电压和属于矩阵行的位置相关的存储单元来对属于矩阵行的目标存储单元进行编程或擦除。 然后，执行刷新位置相关单元的刷新操作。