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    METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK
    1.
    发明申请
    METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK 有权

    公开(公告)号：US20250117642A1

    公开(公告)日：2025-04-10

    申请号：US18983284

    申请日：2024-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Win-San KHWA ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chien-Yin LIU

    IPC: G06N3/063 ,  G06N3/08 ,  G11C7/10 ,  G11C11/54 ,  G11C29/04

    Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

    NOVEL MEMORY DEVICE
    4.
    发明申请
    NOVEL MEMORY DEVICE 有权

    公开(公告)号：US20210090672A1

    公开(公告)日：2021-03-25

    申请号：US17111323

    申请日：2020-12-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Chien-Yin LIU ,  Yi-Chun SHIH

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10

    Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.

    NOVEL MEMORY DEVICE
    5.
    发明申请
    NOVEL MEMORY DEVICE 审中-公开

    公开(公告)号：US20190163568A1

    公开(公告)日：2019-05-30

    申请号：US15965883

    申请日：2018-04-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Yin LIU ,  Yu-Der CHIH ,  Hsueh-Chu YANG ,  Jonathan Tehan CHEN ,  Kuan-Chun CHEN

    IPC: G06F11/10 ,  G11C16/26 ,  G11C11/56 ,  G11C29/42 ,  G11C29/52

    Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N−1 groups and the plurality of parity bits form a first group different from the N−1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N−1 groups; and providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N−1 groups.

    MEMORY DEVICES
    7.
    发明申请
    MEMORY DEVICES 有权
    内存设备

    公开(公告)号：US20160035398A1

    公开(公告)日：2016-02-04

    申请号：US14881492

    申请日：2015-10-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yue-Der CHIH ,  Cheng-Hsiung KUO ,  Gu-Huan LI ,  Chien-Yin LIU

    IPC: G11C7/20 ,  G11C5/02

    CPC classification number: G11C7/20 ,  G11C5/02 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/406 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

    Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed

    Abstract translation: 公开了一种用于具有刷新操作的存储器单元编程和擦除的方法和系统。 该系统包括选择模块，处理模块和刷新模块。 在该方法中，首先，选择来自存储装置中的多个存储单元的目标存储单元。 此后，通过对目标存储单元施加选择电压和属于矩阵行的位置相关的存储单元来对属于矩阵行的目标存储单元进行编程或擦除。 然后，执行刷新位置相关单元的刷新操作

    MEMORY DEVICES
    8.
    发明申请
    MEMORY DEVICES 有权
    内存设备

    公开(公告)号：US20150117131A1

    公开(公告)日：2015-04-30

    申请号：US14067907

    申请日：2013-10-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yue-Der CHIH ,  Cheng-Hsiung KUO ,  Gu-Huan LI ,  Chien-Yin LIU

    IPC: G11C7/00 ,  G11C5/02

    CPC classification number: G11C7/20 ,  G11C5/02 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/406 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

    Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.

    Abstract translation: 公开了一种用于具有刷新操作的存储器单元编程和擦除的方法和系统。 该系统包括选择模块，处理模块和刷新模块。 在该方法中，首先，选择来自存储装置中的多个存储单元的目标存储单元。 此后，通过对目标存储单元施加选择电压和属于矩阵行的位置相关的存储单元来对属于矩阵行的目标存储单元进行编程或擦除。 然后，执行刷新位置相关单元的刷新操作。

    NOVEL MEMORY DEVICE
    10.
    发明申请
    NOVEL MEMORY DEVICE 有权

    公开(公告)号：US20210224154A1

    公开(公告)日：2021-07-22

    申请号：US17222919

    申请日：2021-04-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Yin LIU ,  Yu-Der CHIH ,  Hsueh-Chih YANG ,  Jonathan Tehan CHEN ,  Kuan-Chun CHEN

    IPC: G06F11/10 ,  G11C16/26 ,  G11C29/42 ,  G11C29/52

    Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N−1 groups and the plurality of parity bits form a first group different from the N−1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N−1 groups; and providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N−1 groups.

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