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    Electromigration sign-off methodology
    11.
    发明授权
    Electromigration sign-off methodology 有权

    公开(公告)号：US10346576B2

    公开(公告)日：2019-07-09

    申请号：US16046142

    申请日：2018-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

    IPC: G06F17/50 ,  H01L21/768 ,  G01R31/28

    Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.

    METAL LINES FOR PREVENTING AC ELECTROMIGRATION
    12.
    发明申请
    METAL LINES FOR PREVENTING AC ELECTROMIGRATION 有权
    用于防止交流电气的金属线

    公开(公告)号：US20150095873A1

    公开(公告)日：2015-04-02

    申请号：US14267537

    申请日：2014-05-01

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chin-Shen Lin ,  Jerry Chang-Jui Kao ,  Nitesh Katta ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Kuo-Nan Yang

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit.

    Abstract translation: 公开了一种包括以下概述的操作的方法。 基于在半导体器件的至少一个设计文件中的金属线的金属部分的波形周期内具有多个峰值的电流的波形函数来确定最大峰值的有效电流脉冲宽度，以计算半导体器件的至少一个设计文件中的占空比 有效电流脉冲宽度和波形周期。 根据金属段的物理特性确定金属段的最大直流极限。 根据最大直流限制和占空比函数之间的比例来确定交流电流（AC EM）电流限制。 当电流的最大峰值不超过AC EM电流限制时，金属部分包括在至少一个设计文件中的物理特性。

    Method for evaluating failure-in-time
    13.
    发明授权
    Method for evaluating failure-in-time 有权

    公开(公告)号：US11366951B2

    公开(公告)日：2022-06-21

    申请号：US17204275

    申请日：2021-03-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Shen Lin ,  Ming-Hsien Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

    IPC: G06F30/398 ,  G06F30/394 ,  G06F30/367

    Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

    Optimized electromigration analysis
    14.
    发明授权
    Optimized electromigration analysis 有权

    公开(公告)号：US11055470B2

    公开(公告)日：2021-07-06

    申请号：US16659134

    申请日：2019-10-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Shen Lin ,  Ching-Shun Yang ,  Hsien Yu-Tseng

    IPC: G06F30/398

    Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

    ELECTRMIGRATION SIGN-OFF METHODOLOGY
    15.
    发明申请
    ELECTRMIGRATION SIGN-OFF METHODOLOGY 审中-公开

    公开(公告)号：US20170141003A1

    公开(公告)日：2017-05-18

    申请号：US15271301

    申请日：2016-09-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

    IPC: H01L21/66 ,  G01R31/28 ,  G06F17/50 ,  H01L21/768

    CPC classification number: G06F17/5072 ,  G01R31/2858 ,  G06F17/5036 ,  G06F17/5081 ,  H01L21/768

    Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present. The use of separate actual temperatures for components on different electrical networks mitigates false EM violations, thereby reducing loss of design overhead.

    ELECTROMIGRATION SIGN-OFF METHODOLOGY
    18.
    发明申请
    ELECTROMIGRATION SIGN-OFF METHODOLOGY 审中-公开

    公开(公告)号：US20180330036A1

    公开(公告)日：2018-11-15

    申请号：US16046142

    申请日：2018-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

    IPC: G06F17/50 ,  H01L21/768 ,  G01R31/28

    CPC classification number: G06F17/5072 ,  G01R31/2858 ,  G06F17/5036 ,  G06F17/5081 ,  H01L21/768

    Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.

    Electromigration sign-off methodology
    19.
    发明授权
    Electromigration sign-off methodology 有权

    公开(公告)号：US10042967B2

    公开(公告)日：2018-08-07

    申请号：US15271301

    申请日：2016-09-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

    IPC: G06F17/00 ,  G06F17/50 ,  H01L21/768 ,  G01R31/28

    Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present. The use of separate actual temperatures for components on different electrical networks mitigates false EM violations, thereby reducing loss of design overhead.

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