公开(公告)号：US11121084B2

公开(公告)日：2021-09-14

申请号：US16526983

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234

Abstract: Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect.

公开(公告)号：US10504873B1

公开(公告)日：2019-12-10

申请号：US16016670

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Ming-Fa Chen

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528 ,  H01L25/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00

Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The metal circuit structure is disposed over a back side of the second die. The protective structure is disposed within the back side of the second die and separates one of a plurality of through-substrate vias (TSVs) of the second die from the metal circuit structure.

公开(公告)号：US11251157B2

公开(公告)日：2022-02-15

申请号：US15939310

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Jung Yang ,  Hsien-Wei Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/66 ,  H01L25/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522

Abstract: Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

公开(公告)号：US11251100B2

公开(公告)日：2022-02-15

申请号：US16877508

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-An Kuo ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

公开(公告)号：US20210090966A1

公开(公告)日：2021-03-25

申请号：US16877508

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-An Kuo ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

公开(公告)号：US20190067226A1

公开(公告)日：2019-02-28

申请号：US15690196

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Jung Yang ,  Ming-Yen Chiu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768

Abstract: An integrated circuit package includes a die, a plurality of conductive vias, an alignment mark and an insulating encapsulation. The die includes a plurality of conductive pads. The conductive vias contacts the conductive pads respectively. The alignment mark is disposed on the die and spaced apart from the conductive vias. The insulating encapsulation encapsulates the die and contacts side surfaces of the conductive vias and the alignment mark.

公开(公告)号：US09048149B2

公开(公告)日：2015-06-02

申请号：US13940626

申请日：2013-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Yu-Chia Lai ,  Hsien-Ming Tu ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Chang-Pin Huang ,  Ching-Jung Yang

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/10125 ,  H01L2224/11015 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

Abstract translation: 封装半导体器件包括半导体衬底，金属焊盘，金属基底，聚合物绝缘层，含铜结构和导电凸块。 金属焊盘和金属基底设置在半导体衬底上。 聚合物绝缘层覆盖金属基底和半导体基底。 含铜结构设置在聚合物绝缘层之上，并且包括支撑结构和钝化后互连（PPI）线。 支撑结构与金属基座对准。 PPI线部分地位于支撑结构内，并且通过支撑结构的开口延伸出，其中支撑结构的顶部升高到高于PPI线的顶部。 导电凸块由支撑结构保持。