公开(公告)号：US20180350948A1

公开(公告)日：2018-12-06

申请号：US16050094

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Han-Wen Liao ,  Xuan-You Yan ,  Yen-Yu Chen ,  Chun-Chih Lin

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L21/32135 ,  H01L21/32137 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

公开(公告)号：US12142664B2

公开(公告)日：2024-11-12

申请号：US17323557

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Han-Wen Liao ,  Xuan-You Yan ,  Yen-Yu Chen ,  Chun-Chih Lin

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

公开(公告)号：US11222788B2

公开(公告)日：2022-01-11

申请号：US17000173

申请日：2020-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Wen Liao ,  Jun-Xiu Liu ,  Chun-Chih Lin

IPC: H01L21/306 ,  H01L21/76 ,  H01L21/67 ,  H01L21/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311

Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.

公开(公告)号：US20210280692A1

公开(公告)日：2021-09-09

申请号：US17323557

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Han-Wen Liao ,  Xuan-You Yan ,  Yen-Yu Chen ,  Chun-Chih Lin

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/423

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

公开(公告)号：US20210159196A1

公开(公告)日：2021-05-27

申请号：US17170624

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/00 ,  H01L21/02

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US20190304939A1

公开(公告)日：2019-10-03

申请号：US15937339

申请日：2018-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/00 ,  H01L21/02

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US20180350614A1

公开(公告)日：2018-12-06

申请号：US15686995

申请日：2017-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Wen Liao ,  Jun Xiu Liu ,  Chun-Chih Lin

IPC: H01L21/306 ,  H01L21/67 ,  H01L21/76

Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.

公开(公告)号：US20230072507A1

公开(公告)日：2023-03-09

申请号：US18055241

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/00 ,  H01L21/02

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US11387123B2

公开(公告)日：2022-07-12

申请号：US16857446

申请日：2020-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Powen Huang ,  Yao-Yuan Shang ,  Kuo-Shu Tseng ,  Yen-Yu Chen ,  Chun-Chih Lin ,  Yi-Ming Dai

IPC: G05B19/418 ,  H01L21/67 ,  H01L21/677 ,  H01L21/673 ,  H01L21/02 ,  G01D7/00 ,  G01D5/00 ,  B08B3/04

Abstract: A method for fault detection in a fabrication facility is provided. The method includes moving a wafer carrier along a predetermined path multiple times using a transportation apparatus. The method also includes collecting data associated with an environmental condition within the wafer carrier or around the wafer carrier using a metrology tool on the predetermined path in a previous movement of the transportation apparatus. The method further includes measuring the environmental condition within the wafer carrier or around the wafer carrier using the metrology tool during the movement of the wafer carrier. In addition, the method includes issuing a warning when the measured environmental condition is outside a range of acceptable values. The range of acceptable values is derived from the data collected in the previous movement of the transportation apparatus.

公开(公告)号：US10446662B2

公开(公告)日：2019-10-15

申请号：US15420580

申请日：2017-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Han-Wen Liao ,  Xuan-You Yan ,  Yen-Yu Chen ,  Chun-Chih Lin

IPC: H01L29/66 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.