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    COMPRESSION METHOD AND SYSTEM FOR USE WITH MULTI-PATTERNING
    12.
    发明申请
    COMPRESSION METHOD AND SYSTEM FOR USE WITH MULTI-PATTERNING 审中-公开
    使用多种方式的压缩方法和系统

    公开(公告)号：US20140053118A1

    公开(公告)日：2014-02-20

    申请号：US14064229

    申请日：2013-10-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu CHEN ,  Chin-Hsiung HSU ,  Wen-Hao CHEN ,  Chung-Hsing WANG

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G03F1/70 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

    Abstract translation: 一种方法包括（a）提供集成电路（IC）布局，其包括通过多图案化表示要形成在IC的单层上或其中的多个电路图案的数据; （b）将所述多个电路图案分成两组或更多组; （c）将每个组内的电路图案分配给相应的掩模以提供掩模分配数据，以在IC上或其单层中形成每组电路图案; （d）压缩掩模分配数据; 以及（e）将压缩的掩模分配数据存储到非暂时的机器可读存储介质，以供配置用于从压缩数据重建掩模分配数据的电子设计自动化工具使用。

    INTEGRATED CIRCUIT WITH MIXED ROW HEIGHTS
    14.
    发明申请
    INTEGRATED CIRCUIT WITH MIXED ROW HEIGHTS 有权

    公开(公告)号：US20250159998A1

    公开(公告)日：2025-05-15

    申请号：US19020097

    申请日：2025-01-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Chung-Hsing WANG ,  Yi-Kan CHENG

    IPC: H10D89/10 ,  G06F111/20 ,  H10D84/85

    Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

    INTEGRATED CIRCUIT WITH THICKER METAL LINES ON LOWER METALLIZATION LAYER
    15.
    发明申请
    INTEGRATED CIRCUIT WITH THICKER METAL LINES ON LOWER METALLIZATION LAYER 有权

    公开(公告)号：US20210390240A1

    公开(公告)日：2021-12-16

    申请号：US17404511

    申请日：2021-08-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuang-Hung CHANG ,  Yuan-Te HOU ,  Chung-Hsing WANG ,  Yung-Chin HOU

    IPC: G06F30/392 ,  G06F30/20 ,  H01L23/528 ,  H01L27/088 ,  G06F30/394 ,  G06F30/327

    Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

    STRETCHABLE LAYOUT DESIGN FOR EUV DEFECT MITIGATION
    17.
    发明申请
    STRETCHABLE LAYOUT DESIGN FOR EUV DEFECT MITIGATION 审中-公开

    公开(公告)号：US20190033707A1

    公开(公告)日：2019-01-31

    申请号：US15882235

    申请日：2018-01-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsing-Lin YANG ,  Chin-Chang HSU ,  Yen-Hung LIN ,  Chung-Hsing WANG ,  Wen-Ju YANG

    IPC: G03F1/72 ,  G03F1/84 ,  G03F7/20 ,  G06F17/50 ,  G03F1/00

    Abstract: A method for mitigating extreme ultraviolet (EUV) mask defects is disclosed. The method includes the steps of providing a wafer blank, identifying a first plurality of defects on the wafer blank, providing an EUV mask design on top of the wafer blank, identifying non-critical blocks with corresponding stretchable zones on the EUV mask design, overlapping the EUV blank with the EUV mask design, identifying a second plurality of defects, the second plurality of defects are solved, identifying a third plurality of defects, the third plurality of defects are not solved, adjusting the relative locations of the EUV mask design and the EUV blank to solve at least one of the third plurality of defects, and adjusting the locations of at least one of the non-critical blocks within corresponding stretchable zones to solve at least one of the third plurality of defects.

    INTEGRATED CIRCUIT WITH MIXED ROW HEIGHTS
    19.
    发明申请
    INTEGRATED CIRCUIT WITH MIXED ROW HEIGHTS 有权

    公开(公告)号：US20220149033A1

    公开(公告)日：2022-05-12

    申请号：US17585402

    申请日：2022-01-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Chung-Hsing WANG ,  Yi-Kan CHENG

    IPC: H01L27/02 ,  H01L27/092

    Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

    METHOD FOR EVALUATING FAILURE-IN-TIME
    20.
    发明申请
    METHOD FOR EVALUATING FAILURE-IN-TIME 有权

    公开(公告)号：US20210200930A1

    公开(公告)日：2021-07-01

    申请号：US17204275

    申请日：2021-03-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Shen LIN ,  Ming-Hsien LIN ,  Kuo-Nan YANG ,  Chung-Hsing WANG

    IPC: G06F30/398 ,  G06F30/394

    Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

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