公开(公告)号：US20240155845A1

公开(公告)日：2024-05-09

申请号：US18413668

申请日：2024-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： TsuChing Yang ,  Hung-Chang Sun ,  Kuo Chang Chiang ,  Sheng-Chih Lai ,  Yu-Wei Jiang

IPC: H10B51/20 ,  G11C11/22 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  G11C11/2255 ,  G11C11/2257 ,  H10B51/10 ,  H10B51/30

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.

公开(公告)号：US20230335432A1

公开(公告)日：2023-10-19

申请号：US18341172

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chang Sun ,  Akira Mineji ,  Ziwei Fang

IPC: H01L21/764 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/266

CPC classification number: H01L21/764 ,  H01L29/515 ,  H01L29/6656 ,  H01L21/26586 ,  H01L21/31144 ,  H01L21/31053 ,  H01L21/266

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having an active region and an isolation region. The semiconductor structure includes gate stacks on the substrate that extend over the active region and the isolation region. The semiconductor structure includes a gate spacer on sidewalls of the gate stacks. The semiconductor structure includes an interlevel dielectric (ILD) layer over the substrate and implanted with one or more dopants, the ILD layer having a top implanted portion over a bottom nonimplanted portion. The top implanted portion seals an air gap between a sidewall of the ILD layer and the gate spacer.

公开(公告)号：US11723210B2

公开(公告)日：2023-08-08

申请号：US17333300

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Feng-Cheng Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Chung-Te Lin

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

公开(公告)号：US20210408045A1

公开(公告)日：2021-12-30

申请号：US17119409

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L27/11597 ,  H01L27/12 ,  G11C11/22 ,  H01L29/66 ,  H01L29/786

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

公开(公告)号：US20200020567A1

公开(公告)日：2020-01-16

申请号：US16262235

申请日：2019-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chang Sun ,  Akira Mineji ,  Ziwei Fang

IPC: H01L21/764 ,  H01L29/51 ,  H01L29/66 ,  H01L21/266 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/265

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

公开(公告)号：US20170207133A1

公开(公告)日：2017-07-20

申请号：US15001364

申请日：2016-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chih-Hao Wang ,  Wei-Hao Wu ,  Hung-Chang Sun ,  Lung-Kun Chu

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/092 ,  H01L29/4966

Abstract: The present disclosure relates to an integrated circuit with a work function metal layer disposed directly on a high-k dielectric layer, and an associated method of formation. In some embodiments, the integrated circuit is formed by forming a first work function metal layer directly on a high-k dielectric layer. Then the first work function metal layer is patterned to be left within a first gate region of a first device region and to be removed within a second gate region of a second device region. Thereby, the first work function metal layer is patterned directly on the high-k dielectric layer, using the high-k dielectric layer as an etch stop layer, and the patterning window is improved.

公开(公告)号：US20250120091A1

公开(公告)日：2025-04-10

申请号：US18985411

申请日：2024-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H10B51/10 ,  H10D30/67

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

公开(公告)号：US20250105054A1

公开(公告)日：2025-03-27

申请号：US18974295

申请日：2024-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chang Sun ,  Akira Mineji ,  Ziwei Fang

IPC: H01L21/764 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/51 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having an active region and an isolation region. The semiconductor structure includes gate stacks on the substrate that extend over the active region and the isolation region. The semiconductor structure includes a gate spacer on sidewalls of the gate stacks. The semiconductor structure includes an interlevel dielectric (ILD) layer over the substrate and implanted with one or more dopants, the ILD layer having a top implanted portion over a bottom nonimplanted portion. The top implanted portion seals an air gap between a sidewall of the ILD layer and the gate spacer.

公开(公告)号：US11903214B2

公开(公告)日：2024-02-13

申请号：US17316167

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： TsuChing Yang ,  Hung-Chang Sun ,  Kuo Chang Chiang ,  Sheng-Chih Lai ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H10B51/30 ,  G11C11/22 ,  H10B51/10

CPC classification number: H10B51/20 ,  G11C11/2255 ,  G11C11/2257 ,  H10B51/10 ,  H10B51/30

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.

公开(公告)号：US11729987B2

公开(公告)日：2023-08-15

申请号：US17119409

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  G11C11/22

CPC classification number: H10B51/20 ,  G11C11/223 ,  H01L27/1225 ,  H01L29/66742 ,  H01L29/7869

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.