公开(公告)号：US20220277789A1

公开(公告)日：2022-09-01

申请号：US17749325

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Shih-Hao Lin ,  Kian-Long Lim

IPC: G11C11/418 ,  G11C11/419

Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.

公开(公告)号：US11211116B2

公开(公告)日：2021-12-28

申请号：US16922270

申请日：2020-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kian-Long Lim ,  Feng-Ming Chang

IPC: G11C11/419 ,  G11C11/418

Abstract: A static random-access memory (SRAM) semiconductor device including a memory unit is provided. The memory unit includes a bit array arranged in rows and columns. The columns are defined by a plurality of bit line pairs connecting to a plurality of memory cells in the column. The memory unit also includes an edge area adjacent an edge row of the bit array, wherein the edge row includes a plurality of dummy memory cells. The memory unit further includes a plurality of bit line drivers adjacent the bit array and opposite the edge area. The bit line drivers are for driving the bit lines with data to the memory cells during a write operation. The dummy memory cells include a write assist circuit for each bit line pair. The write assist circuit is used for facilitating the writing of the data on the bit line pairs to the memory cells.

公开(公告)号：US20210305262A1

公开(公告)日：2021-09-30

申请号：US17248112

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  G11C11/418

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US20210098058A1

公开(公告)日：2021-04-01

申请号：US16922270

申请日：2020-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kian-Long Lim ,  Feng-Ming Chang

IPC: G11C11/419 ,  G11C11/418

Abstract: A static random-access memory (SRAM) semiconductor device including a memory unit is provided. The memory unit includes a bit array arranged in rows and columns. The columns are defined by a plurality of bit line pairs connecting to a plurality of memory cells in the column. The memory unit also includes an edge area adjacent an edge row of the bit array, wherein the edge row includes a plurality of dummy memory cells. The memory unit further includes a plurality of bit line drivers adjacent the bit array and opposite the edge area. The bit line drivers are for driving the bit lines with data to the memory cells during a write operation. The dummy memory cells include a write assist circuit for each bit line pair. The write assist circuit is used for facilitating the writing of the data on the bit line pairs to the memory cells.

公开(公告)号：US10714168B2

公开(公告)日：2020-07-14

申请号：US16725409

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Kian-Long Lim ,  Feng-Ming Chang ,  Lien-Jung Hung

IPC: G11C11/412 ,  H01L27/02 ,  H01L27/11 ,  H01L27/092 ,  H01L29/78 ,  H01L27/12

Abstract: A static random access memory (SRAM) array is provided. The SRAM array includes a first bit cell array and a second bit cell array arranged along a first direction. The SRAM array includes a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The SRAM array includes a deep N-type well region underlying and connected to the first N-type well region and the second N-type well region.

公开(公告)号：US12190943B2

公开(公告)日：2025-01-07

申请号：US18336816

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan Chang ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Kian-Long Lim

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

公开(公告)号：US20240332089A1

公开(公告)日：2024-10-03

申请号：US18741998

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/31155 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US20240290886A1

公开(公告)日：2024-08-29

申请号：US18654766

申请日：2024-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Lien Jung Hung

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/66818

Abstract: A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

公开(公告)号：US12027425B2

公开(公告)日：2024-07-02

申请号：US17877221

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/31155 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US11937416B2

公开(公告)日：2024-03-19

申请号：US17750649

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.