公开(公告)号：US20170365472A1

公开(公告)日：2017-12-21

申请号：US15696498

申请日：2017-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC: H01L21/033 ,  H01L27/11

Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material.

公开(公告)号：US12002710B2

公开(公告)日：2024-06-04

申请号：US16924200

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsin Chan ,  Jiing-Feng Yang ,  Kuan-Wei Huang ,  Meng-Shu Lin ,  Yu-Yu Chen ,  Chia-Wei Wu ,  Chang-Wen Chen ,  Wei-Hao Lin ,  Ching-Yu Chang

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/528

Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

公开(公告)号：US20220384201A1

公开(公告)日：2022-12-01

申请号：US17883930

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/311

Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

公开(公告)号：US20220367204A1

公开(公告)日：2022-11-17

申请号：US17513708

申请日：2021-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033

Abstract: A method for manufacturing a semiconductor device includes depositing a first hard mask layer and a first dielectric layer over a substrate, forming a patterned layer over the first dielectric layer, forming a second hard mask layer over the patterned layer, patterning the second hard mask layer to remove first horizontal portions of the second hard mask layer and leave second portions of the second hard mask layer along sidewalls of the patterned layer, etching a trench in the first dielectric layer using the second portions of the second hard mask layer and the patterned layer as an etching mask, depositing a first gap-filling material in the trench and patterning the first hard mask layer using the first gap-filling material, the patterned layer, and the second portions of the second hard mask layer as a mask.

公开(公告)号：US20220310441A1

公开(公告)日：2022-09-29

申请号：US17369497

申请日：2021-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Nien Su ,  Yu-Yu Chen ,  Kuan-Wei Huang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

公开(公告)号：US09698016B2

公开(公告)日：2017-07-04

申请号：US15202842

申请日：2016-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC: H01L21/44 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  H01L21/461 ,  H01L21/76816 ,  H01L27/1116

Abstract: The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a first cut layer over a hard mask having a first layer and an underlying second layer. A first plurality of openings are formed within the first layer and expose the second layer at a first plurality of positions. Two or more of the first plurality of openings are separated by the first cut layer. A spacer material is selectively formed onto sidewalls of the first plurality of openings within the first layer. A second plurality of openings are then formed within the first layer. The second plurality of openings are separated by a second cut layer including the spacer material and expose the second layer at a second plurality of positions. The second layer is etched according to the first layer and the spacer material.

公开(公告)号：US12191158B2

公开(公告)日：2025-01-07

申请号：US17513708

申请日：2021-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/768

Abstract: A method for manufacturing a semiconductor device includes depositing a first hard mask layer and a first dielectric layer over a substrate, forming a patterned layer over the first dielectric layer, forming a second hard mask layer over the patterned layer, patterning the second hard mask layer to remove first horizontal portions of the second hard mask layer and leave second portions of the second hard mask layer along sidewalls of the patterned layer, etching a trench in the first dielectric layer using the second portions of the second hard mask layer and the patterned layer as an etching mask, depositing a first gap-filling material in the trench and patterning the first hard mask layer using the first gap-filling material, the patterned layer, and the second portions of the second hard mask layer as a mask.

公开(公告)号：US11521857B2

公开(公告)日：2022-12-06

申请号：US16163878

申请日：2018-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC: H01L21/3105 ,  H01L21/033 ,  H01L21/768 ,  H01L27/11 ,  H01L21/461

Abstract: The present disclosure, in some embodiments, relates to a method of performing an etch process. The method is performed by forming a first plurality of openings defined by first sidewalls of a mask disposed over a substrate. A cut layer is between two of the first plurality of openings. A spacer is formed onto the first sidewalls of the mask and a second plurality of openings are formed. The second plurality of openings are defined by second sidewalls of the mask and are separated by the spacer. The substrate is etched according to the mask and the spacer.

公开(公告)号：US11037789B2

公开(公告)日：2021-06-15

申请号：US16705536

申请日：2019-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Chia-Ying Lee ,  Ming-Chung Liang

IPC: H01L21/033 ,  H01L27/11

Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material over an underlying layer. The spacer material has sidewalls defining a first trench. A cut material is formed over the spacer material and within the first trench. The cut material separates the trench into a pair of trench segments having ends separated by the cut material. The underlying layer is patterned according to the spacer material and the cut material.

公开(公告)号：US10672614B2

公开(公告)日：2020-06-02

申请号：US16203955

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Chia-Nan Lin

IPC: H01L21/306 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/3115 ,  H01L21/3215

Abstract: Embodiments described herein relate generally to methods for etching structures and the structures formed thereby. In some embodiments, an etch selectivity between a first portion of a material and a second portion of the material is increased. Increasing the etch selectivity includes performing an anisotropic treatment, such as an anisotropic ion implantation, on the material to treat the first portion of the material, and the second portion of the material remains untreated after the anisotropic treatment. After increasing the etch selectivity, the first portion of the material is etched. The etching may be a wet or dry etch, and may further be isotropic or anisotropic.