公开(公告)号：US20210375711A1

公开(公告)日：2021-12-02

申请号：US16885304

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Wei Shen ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: Semiconductor package includes interposer, dies, encapsulant. Each die includes active surface, backside surface, side surfaces. Backside surface is opposite to active surface. Side surfaces join active surface to backside surface. Encapsulant includes first material and laterally wraps dies. Dies are electrically connected to interposer and disposed side by side on interposer with respective backside surfaces facing away from interposer. At least one die includes an outer corner. A rounded corner structure is formed at the outer corner. The rounded corner structure includes second material different from first material. The outer corner is formed by backside surface and a pair of adjacent side surfaces of the at least one die. The side surfaces of the pair have a common first edge. Each side surface of the pair does not face other dies and has a second edge in common with backside surface of the at least one die.

公开(公告)号：US20210320097A1

公开(公告)日：2021-10-14

申请号：US17355433

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L25/18

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US12087733B2

公开(公告)日：2024-09-10

申请号：US17383911

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Li-Chung Kuo ,  Sung-Hui Huang ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0655 ,  H01L23/3185 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L25/18 ,  H01L2224/32057 ,  H01L2224/33051 ,  H01L2224/33152 ,  H01L2224/3316 ,  H01L2224/73204 ,  H01L2224/9211 ,  H01L2224/92125

Abstract: A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

公开(公告)号：US20230378132A1

公开(公告)日：2023-11-23

申请号：US18150525

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Wei Shen ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Sen-Bor Jan ,  Szu-Po Huang ,  Kuan-Yu Huang

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/0655 ,  H01L21/565 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/05 ,  H01L21/76895 ,  H01L23/49827 ,  H01L2224/05569 ,  H01L2224/16146 ,  H01L2924/3511 ,  H01L24/16

Abstract: A semiconductor device includes: a substrate; a plurality of dies attached to a first side of the substrate; a molding material on the first side of the substrate around the plurality of dies; a first redistribution structure on a second side of the substrate opposing the first side, where the first redistribution structure includes dielectric layers and conductive features in the dielectric layers, where the conductive features include conductive lines, vias, and dummy metal patterns isolated from the conductive lines and the vias; and conductive connectors attached to a first surface of the first redistribution structure facing away from the substrate.

公开(公告)号：US11454773B2

公开(公告)日：2022-09-27

申请号：US17121060

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/48

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US11450580B2

公开(公告)日：2022-09-20

申请号：US16920408

申请日：2020-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chien-Yuan Huang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/04 ,  H01L21/52 ,  H01L23/31

Abstract: A semiconductor structure and a method for fabricating the same are disclosed. A semiconductor structure includes a first substrate, a package, a second substrate, and a lid. The package is attached to a first side of the first substrate. The second substrate is attached to a second side of the first substrate. The lid is connected to the first substrate and the second substrate. The lid includes a ring part over the first side of the first substrate. The ring part and the first substrate define a space and the package is accommodated in the space. The lid further includes a plurality of overhang parts which extend from corner sidewalls of the ring part toward the second substrate to cover corner sidewalls of the first substrate.

公开(公告)号：US11222867B1

公开(公告)日：2022-01-11

申请号：US16924203

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hui Huang ,  Shang-Yun Hou ,  Kuan-Yu Huang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package includes a first die, a second die, a semiconductor frame, and a reinforcement structure. The first di has a first surface and a second surface opposite to the first surface. The first die includes grooves on the first surface. The second die and the semiconductor frame are disposed side by side over the first surface of the first die. The semiconductor frame has at least one notch exposing the grooves of the first die. The reinforcement structure is disposed on the second surface of the first die. The reinforcement structure includes a first portion aligned with the grooves.

公开(公告)号：US20210210400A1

公开(公告)日：2021-07-08

申请号：US17208694

申请日：2021-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US12253729B2

公开(公告)日：2025-03-18

申请号：US17952681

申请日：2022-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/48

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US12237288B2

公开(公告)日：2025-02-25

申请号：US18446732

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Shu Chia Hsu ,  Yu-Yun Huang ,  Wen-Yao Chang ,  Yu-Jen Cheng

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.