公开(公告)号：US11374105B2

公开(公告)日：2022-06-28

申请号：US16835759

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

公开(公告)号：US11201094B2

公开(公告)日：2021-12-14

申请号：US16372021

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Wei-Hao Wu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/088 ,  H01L21/3115 ,  H01L27/092 ,  H01L21/8234

Abstract: A method of fabricating an integrated circuit (IC) structure, includes forming a gate trench that exposes a portion of each of a plurality of fins and forming a threshold voltage (Vt) tuning dielectric layer in the gate trench over the plurality of fins. Properties of the Vt tuning dielectric layer are adjusted during the forming to achieve a different Vt for each of the plurality of fins. The method also includes forming a glue metal layer over the Vt tuning dielectric layer; and forming a fill metal layer over the glue metal layer. The fill metal layer has a substantially uniform thickness over top surfaces of the plurality of fins.

公开(公告)号：US11145734B1

公开(公告)日：2021-10-12

申请号：US16915784

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; a gate structure wrapping each of the semiconductor layers; a spacer structure wrapping an edge portion of each of the semiconductor layers; and a dummy fin structure contacting a sidewall of the gate structure, wherein the dummy fin structure is separated from a sidewall of the spacer structure by a dielectric liner.

公开(公告)号：US09960085B2

公开(公告)日：2018-05-01

申请号：US15001364

申请日：2016-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chih-Hao Wang ,  Wei-Hao Wu ,  Hung-Chang Sun ,  Lung-Kun Chu

IPC: H01L21/338 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/092 ,  H01L29/4966

Abstract: The present disclosure relates to an integrated circuit with a work function metal layer disposed directly on a high-k dielectric layer, and an associated method of formation. In some embodiments, the integrated circuit is formed by forming a first work function metal layer directly on a high-k dielectric layer. Then the first work function metal layer is patterned to be left within a first gate region of a first device region and to be removed within a second gate region of a second device region. Thereby, the first work function metal layer is patterned directly on the high-k dielectric layer, using the high-k dielectric layer as an etch stop layer, and the patterning window is improved.

公开(公告)号：US20250120166A1

公开(公告)日：2025-04-10

申请号：US18982010

申请日：2024-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

公开(公告)号：US12266544B2

公开(公告)日：2025-04-01

申请号：US18645181

申请日：2024-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Jia-Ni Yu ,  Chun-Fu Lu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/00 ,  H01L21/475 ,  H01L21/4757 ,  H01L21/477 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

公开(公告)号：US12170231B2

公开(公告)日：2024-12-17

申请号：US17815079

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

公开(公告)号：US12087772B2

公开(公告)日：2024-09-10

申请号：US17476140

申请日：2021-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/02 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/0259 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.

公开(公告)号：US20230411219A1

公开(公告)日：2023-12-21

申请号：US18151598

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L21/823857 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L21/823807 ,  H01L29/66439 ,  H01L29/6684 ,  H01L29/4908

Abstract: A semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; a second gate dielectric layer disposed over the second channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and the second gate dielectric layer includes a second dipole dopant embedded therein. A boundary between the first gate dielectric layer and the second gat dielectric layer contains the first dipole dopant and the second dipole dopant.

公开(公告)号：US11848368B2

公开(公告)日：2023-12-19

申请号：US17504206

申请日：2021-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/28061 ,  H01L21/28088 ,  H01L21/32051 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0665 ,  H01L2029/7858

Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.