公开(公告)号：US10263073B2

公开(公告)日：2019-04-16

申请号：US15397508

申请日：2017-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Gerben Doornbos ,  Matthias Passlack ,  Martin Christopher Holland

IPC: H01L21/306 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/20 ,  B82Y10/00 ,  H01L29/10 ,  H01L29/04

Abstract: A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.

公开(公告)号：US12051702B2

公开(公告)日：2024-07-30

申请号：US18167776

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1248 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78675 ,  H01L29/78696 ,  H01L21/02645 ,  H01L21/02675 ,  H01L29/78618

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US20230197445A1

公开(公告)日：2023-06-22

申请号：US18167776

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/02488 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78675 ,  H01L21/02645 ,  H01L21/02675 ,  H01L29/66757 ,  H01L29/78648 ,  H01L29/78696 ,  H01L21/02532 ,  H01L21/02592

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US11557726B2

公开(公告)日：2023-01-17

申请号：US17068736

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Marcus Johannes Henricus Van Dal ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L21/00 ,  H01L51/00 ,  C23C16/455 ,  C23C16/56 ,  H01L23/544 ,  H01L51/05

Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.

公开(公告)号：US11437594B2

公开(公告)日：2022-09-06

申请号：US16940321

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Timothy Vasen ,  Mark Van Dal ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L51/05 ,  H01L27/28 ,  H01L51/00

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

公开(公告)号：US11349022B2

公开(公告)日：2022-05-31

申请号：US16889600

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/66 ,  H01L29/775 ,  H01L29/205 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US11088246B2

公开(公告)日：2021-08-10

申请号：US16516181

申请日：2019-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Matthias Passlack ,  Marcus Johannes Henricus Van Dal ,  Timothy Vasen ,  Georgios Vellianitis

IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

公开(公告)号：US20210119131A1

公开(公告)日：2021-04-22

申请号：US16656583

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Chao-Ching Cheng ,  Matthias Passlack ,  Martin Christopher Holland ,  Tse-An Chen ,  Lain-Jong Li

IPC: H01L51/00 ,  H01L51/05

Abstract: A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

公开(公告)号：US10923659B2

公开(公告)日：2021-02-16

申请号：US16401042

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Marcus Johannes Henricus van Dal ,  Matthias Passlack

IPC: H01L21/00 ,  H01L51/00 ,  C23C16/455 ,  C23C16/56 ,  H01L23/544 ,  H01L51/05

Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.

公开(公告)号：US20200303530A1

公开(公告)日：2020-09-24

申请号：US16889600

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/775 ,  H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.