公开(公告)号：US20240387317A1

公开(公告)日：2024-11-21

申请号：US18788832

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

公开(公告)号：US12094810B2

公开(公告)日：2024-09-17

申请号：US18340387

申请日：2023-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/81815

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

公开(公告)号：US11764169B2

公开(公告)日：2023-09-19

申请号：US17739990

申请日：2022-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H01L23/00 ,  H01L23/36 ,  H01L23/40 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/36 ,  H01L23/3128 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A semiconductor device package includes a die, a molding layer, a heat spreader lid, and a warpage control adhesive layer. The molding layer surrounds the die. The molding layer has a first edge and a second edge at least partially defining a corner of the molding layer. The heat spreader lid covers the molding layer and the die. The warpage control adhesive layer is between the heat spreader lid and the molding layer. The warpage control adhesive layer is at the corner of the molding layer and has a bar shape in a top view, and the warpage control adhesive layer extends from the first edge toward the second edge of the molding layer.

公开(公告)号：US11728256B2

公开(公告)日：2023-08-15

申请号：US17808827

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/81815

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

公开(公告)号：US11705420B2

公开(公告)日：2023-07-18

申请号：US17178460

申请日：2021-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Yen Lee ,  Chia-Kuei Hsu ,  Shang-Lun Tsai ,  Ming-Chih Yew ,  Po-Yao Lin

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L2224/0235 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/1147 ,  H01L2224/13014 ,  H01L2224/1411 ,  H01L2225/06517

Abstract: A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.

公开(公告)号：US11652037B2

公开(公告)日：2023-05-16

申请号：US17139775

申请日：2020-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Chen Lai ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L25/18 ,  H01L23/49816 ,  H01L23/5383 ,  H01L2224/16227 ,  H01L2224/81192

Abstract: Semiconductor devices having improved under-bump metallization layouts and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes an IC die; an interconnect structure coupled to the IC die and including a metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer over the dielectric layer opposite the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM over the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, a centerline of the via portion and a second centerline of the second via portion being misaligned with a third centerline of the UBM, the centerline and the second centerline being on opposite sides of the third centerline.

公开(公告)号：US20230024043A1

公开(公告)日：2023-01-26

申请号：US17698611

申请日：2022-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/367 ,  H01L25/065 ,  H01L21/48

Abstract: Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

公开(公告)号：US11062997B2

公开(公告)日：2021-07-13

申请号：US16180511

申请日：2018-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Lin ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Chuang

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31 ,  H01L21/768

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive pillar over a redistribution structure. The method includes bonding a chip to the redistribution structure. The method includes forming a molding layer over the redistribution structure. The molding layer surrounds the conductive pillar and the chip, and the conductive pillar passes through the molding layer. The method includes forming a cap layer over the molding layer and the conductive pillar. The cap layer has a through hole exposing the conductive pillar, and the cap layer includes fibers. The method includes forming a conductive via structure in the through hole. The conductive via structure is connected to the conductive pillar.

公开(公告)号：US09831190B2

公开(公告)日：2017-11-28

申请号：US14151217

申请日：2014-01-09

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H01L23/00 ,  H01L23/40 ,  H01L23/34 ,  H01L23/36 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.

公开(公告)号：US12255078B2

公开(公告)日：2025-03-18

申请号：US18447443

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Po-Yao Lin ,  Chien-Sheng Chen ,  Shin-Puu Jeng

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/31

Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.