公开(公告)号：US20230402402A1

公开(公告)日：2023-12-14

申请号：US17663683

申请日：2022-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chien Hung Chen ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L21/563

Abstract: A semiconductor package including a recessed stiffener ring and a method of forming are provided. The semiconductor package may include a substrate, a semiconductor die bonded to the substrate, an underfill between the semiconductor die and the substrate, and a stiffener ring attached to the substrate, wherein the stiffener ring encircles the semiconductor die in a top view. The stiffener ring may include a recess that faces the semiconductor die.

公开(公告)号：US20230335477A1

公开(公告)日：2023-10-19

申请号：US18340387

申请日：2023-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/81815

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

公开(公告)号：US20230317661A1

公开(公告)日：2023-10-05

申请号：US18327252

申请日：2023-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Yen Lee ,  Chia-Kuei Hsu ,  Shang-Lun Tsai ,  Ming-Chih Yew ,  Po-Yao Lin

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L2224/02311 ,  H01L2225/06517 ,  H01L2224/02381 ,  H01L2224/1147 ,  H01L2224/13014 ,  H01L2224/0235 ,  H01L2224/1411 ,  H01L2224/02331

Abstract: A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.

公开(公告)号：US11749644B2

公开(公告)日：2023-09-05

申请号：US17652764

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L23/3128

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US20230253303A1

公开(公告)日：2023-08-10

申请号：US18302500

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Chen Lai ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L25/18 ,  H01L23/49816 ,  H01L23/5383

Abstract: Semiconductor devices having improved under-bump metallization layouts and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes an IC die; an interconnect structure coupled to the IC die and including a metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer over the dielectric layer opposite the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM over the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, a centerline of the via portion and a second centerline of the second via portion being misaligned with a third centerline of the UBM, the centerline and the second centerline being on opposite sides of the third centerline.

公开(公告)号：US11721644B2

公开(公告)日：2023-08-08

申请号：US17372694

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Hung Chen ,  Shu-Shen Yeh ,  Po-Chen Lai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/58 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/16 ,  H01L23/3185 ,  H01L23/585 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

公开(公告)号：US11682602B2

公开(公告)日：2023-06-20

申请号：US17246035

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3675 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16227

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

公开(公告)号：US11670601B2

公开(公告)日：2023-06-06

申请号：US17126957

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/35121

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US11508710B2

公开(公告)日：2022-11-22

申请号：US16884046

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Lin ,  Cheng-Yi Hong ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng ,  Shu-Shen Yeh ,  Kuang-Chun Lee

IPC: H01L25/18 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/24 ,  H01L25/00 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L23/373

Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.

公开(公告)号：US20220359354A1

公开(公告)日：2022-11-10

申请号：US17813820

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00 ,  G06F30/3953

Abstract: A structure includes a first package component including a first conductive pad, and a second package component overlying the first package component. The second package component includes a surface dielectric layer, and a conductive bump protruding lower than the surface dielectric layer. The first conductive bump includes a first sidewall facing away from a center of the first package component, and a second sidewall facing toward the center. A solder bump joins the first conductive pad to the first conductive bump. The solder bump contacts the first sidewall. An underfill is between the first package component and the second package component, and the underfill contacts the second sidewall.