公开(公告)号：US20200219868A1

公开(公告)日：2020-07-09

申请号：US16817984

申请日：2020-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chou Tseng ,  Ming-Fu Tsai ,  Tzu-Heng Chang

IPC: H01L27/02 ,  H01L23/525 ,  H01L23/498 ,  H01L21/66 ,  G01R31/26 ,  G01R31/00

Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.

公开(公告)号：US11742236B2

公开(公告)日：2023-08-29

申请号：US17106553

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Jen-Chou Tseng ,  Chia-Wei Hsu ,  Ming-Fu Tsai

IPC: H01L21/762 ,  H01L27/02 ,  H01L29/06 ,  H01L29/73 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L27/0259 ,  H01L29/0649 ,  H01L29/66234 ,  H01L29/73

Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.

公开(公告)号：US11710962B2

公开(公告)日：2023-07-25

申请号：US17827776

申请日：2022-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Yu-Ti Su ,  Chia-Wei Hsu ,  Ming-Fu Tsai ,  Shu-Yu Su ,  Li-Wei Chu ,  Jam-Wem Lee ,  Chia-Jung Chang ,  Hsiang-Hui Cheng

IPC: H02H9/04 ,  G01R31/00 ,  H02H1/00

CPC classification number: H02H9/046 ,  G01R31/001 ,  H02H1/0007

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

公开(公告)号：US11676959B2

公开(公告)日：2023-06-13

申请号：US17836899

申请日：2022-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fu Tsai ,  Tzu-Heng Chang ,  Yu-Ti Su ,  Kai-Ping Huang

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L27/0285 ,  H01L27/0296 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

公开(公告)号：US11282831B2

公开(公告)日：2022-03-22

申请号：US16575091

申请日：2019-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Li-Wei Chu ,  Ming-Fu Tsai ,  Jam-Wem Lee ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/87 ,  H01L29/86 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L23/60 ,  H01L23/62 ,  H01L29/747 ,  H01L29/861

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

公开(公告)号：US10957687B2

公开(公告)日：2021-03-23

申请号：US16817984

申请日：2020-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chou Tseng ,  Ming-Fu Tsai ,  Tzu-Heng Chang

IPC: H01L27/02 ,  H01L21/66 ,  G01R31/00 ,  G01R31/26 ,  H01L23/498 ,  H01L23/525

Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.