公开(公告)号：US11855221B2

公开(公告)日：2023-12-26

申请号：US17874466

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Ming-Shiang Lin ,  Jin Cai

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/02321 ,  H01L29/517 ,  H01L29/66795

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

公开(公告)号：US11387360B2

公开(公告)日：2022-07-12

申请号：US16874526

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US10818562B2

公开(公告)日：2020-10-27

申请号：US16020860

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Shiang Lin ,  Chia-Cheng Ho ,  Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chih-Sheng Chang

IPC: H01L21/76 ,  H01L29/78 ,  H01L21/66 ,  G01R27/26

Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.

公开(公告)号：US20200127138A1

公开(公告)日：2020-04-23

申请号：US16255334

申请日：2019-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Chia-Cheng Ho ,  Tzu-Chung Wang ,  Tung Ying Lee ,  Jin Cai ,  Ming-Shiang Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/51

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US11942380B2

公开(公告)日：2024-03-26

申请号：US17080625

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Shiang Lin ,  Chia-Cheng Ho ,  Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chih-Sheng Chang

IPC: H01L29/417 ,  G01R27/26 ,  H01L21/283 ,  H01L21/306 ,  H01L21/324 ,  H01L21/66 ,  H01L29/66

CPC classification number: H01L22/14 ,  G01R27/2617 ,  H01L22/34

Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

公开(公告)号：US20230387310A1

公开(公告)日：2023-11-30

申请号：US18447453

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Ming-Shiang Lin ,  Jin Cai

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/517 ,  H01L29/66795 ,  H01L21/02181 ,  H01L21/02321

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) appl

公开(公告)号：US10797174B2

公开(公告)日：2020-10-06

申请号：US16104692

申请日：2018-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Tai Chang ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Tzu-Chung Wang ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/033 ,  H01L21/02 ,  H01L23/532

Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.

公开(公告)号：US20200273997A1

公开(公告)日：2020-08-27

申请号：US16874539

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US10395937B2

公开(公告)日：2019-08-27

申请号：US15689334

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Dian-Hau Chen ,  Han-Ting Tsai ,  Tsung-Lin Lee ,  Chia-Cheng Ho ,  Ming-Shiang Lin

IPC: H01L21/308 ,  H01L21/311 ,  H01L27/092 ,  H01L21/3115

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.