公开(公告)号：US11682654B2

公开(公告)日：2023-06-20

申请号：US16718073

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Li-Hsien Huang ,  Ta-Hsuan Lin ,  Ming-Shih Yeh

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827

Abstract: A semiconductor structure includes a semiconductor structure includes a semiconductor die, an insulating encapsulation, a passivation layer and conductive elements. The semiconductor die includes a sensor device and a semiconductor substrate with a first region and a second region adjacent to the first region, and the sensor device is embedded in the semiconductor substrate within the first region. The insulating encapsulation laterally encapsulates the semiconductor die and covers a sidewall of the semiconductor die. The passivation layer is located on the semiconductor die, wherein a recess penetrates through the passivation layer over the first region and is overlapped with the sensor device. The conductive elements are located on the passivation layer over the second region and are electrically connected to the semiconductor die, wherein the passivation layer is between the insulating encapsulation and the conductive elements.

公开(公告)号：US20220013461A1

公开(公告)日：2022-01-13

申请号：US16924201

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  An-Jhih Su ,  Der-Chyang Yeh ,  Shih-Guo Shen ,  Chia-Nan Yuan ,  Ming-Shih Yeh

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.

公开(公告)号：US20210183813A1

公开(公告)日：2021-06-17

申请号：US16718073

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Li-Hsien Huang ,  Ta-Hsuan Lin ,  Ming-Shih Yeh

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor structure includes a semiconductor structure includes a semiconductor die, an insulating encapsulation, a passivation layer and conductive elements. The semiconductor die includes a sensor device and a semiconductor substrate with a first region and a second region adjacent to the first region, and the sensor device is embedded in the semiconductor substrate within the first region. The insulating encapsulation laterally encapsulates the semiconductor die and covers a sidewall of the semiconductor die. The passivation layer is located on the semiconductor die, wherein a recess penetrates through the passivation layer over the first region and is overlapped with the sensor device. The conductive elements are located on the passivation layer over the second region and are electrically connected to the semiconductor die, wherein the passivation layer is between the insulating encapsulation and the conductive elements.

公开(公告)号：US20210066263A1

公开(公告)日：2021-03-04

申请号：US16795523

申请日：2020-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Li-Hsien Huang ,  Tien-Chung Yang ,  Ming-Shih Yeh

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.

公开(公告)号：US10756037B2

公开(公告)日：2020-08-25

申请号：US15980662

申请日：2018-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Yueh-Ting Lin ,  Ming-Shih Yeh

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/58 ,  H01L21/56 ,  H01L21/66

Abstract: A package structure including a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of conductive terminals is provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads and a plurality of conductive strips. The conductive pads are disposed on and connected to the plurality of conductive pads, wherein each of the conductive strips is physically connected to at least two conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant and the semiconductor die, wherein the redistribution layer is electrically connected to the plurality of conductive strips. The plurality of conductive terminals is disposed on the redistribution layer.

公开(公告)号：US20200251456A1

公开(公告)日：2020-08-06

申请号：US16857161

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Po-Hao Tsai ,  Ming-Shih Yeh ,  Ta-Wei Liu

IPC: H01L25/10 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

公开(公告)号：US10290610B2

公开(公告)日：2019-05-14

申请号：US15688893

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Li-Hui Cheng ,  Po-Hao Tsai ,  Wei-Yu Chen ,  Ming-Shih Yeh

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L25/00 ,  H01L23/522 ,  H01L23/498

Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.

公开(公告)号：US20190131283A1

公开(公告)日：2019-05-02

申请号：US15795280

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Po-Hao Tsai ,  Ming-Shih Yeh ,  Ta-Wei Liu

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

公开(公告)号：US20190067249A1

公开(公告)日：2019-02-28

申请号：US15688893

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Li-Hui Cheng ,  Po-Hao Tsai ,  Wei-Yu Chen ,  Ming-Shih Yeh

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L23/522 ,  H01L25/00

Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.

公开(公告)号：US20190035772A1

公开(公告)日：2019-01-31

申请号：US15660968

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Ming-Chih Yew ,  Yi-Jen Lai ,  Ming-Shih Yeh

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/544 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.