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    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210066263A1

    公开(公告)日：2021-03-04

    申请号：US16795523

    申请日：2020-02-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Li-Hsien Huang ,  Tien-Chung Yang ,  Ming-Shih Yeh

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00

    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.

    Semiconductor package and manufacturing method thereof
    7.
    发明授权
    Semiconductor package and manufacturing method thereof 有权

    公开(公告)号：US11145633B2

    公开(公告)日：2021-10-12

    申请号：US16795523

    申请日：2020-02-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Li-Hsien Huang ,  Tien-Chung Yang ,  Ming-Shih Yeh

    IPC: H01L25/10 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.

    Package structure and manufacturing method thereof
    8.
    发明授权
    Package structure and manufacturing method thereof 有权

    公开(公告)号：US10276542B2

    公开(公告)日：2019-04-30

    申请号：US15215605

    申请日：2016-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Hsien Huang ,  An-Jhih Su ,  Hsien-Wei Chen ,  Hua-Wei Tseng ,  Jo-Mei Wang ,  Tien-Chung Yang ,  Kuan-Chung Lu

    IPC: H01L25/065 ,  H01L23/552 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer.

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