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    Dislocation Stress Memorization Technique (DSMT) on Epitaxial Channel Devices
    12.
    发明申请
    Dislocation Stress Memorization Technique (DSMT) on Epitaxial Channel Devices 有权
    位错应力记忆技术（DSMT）在外延通道器件上的应用

    公开(公告)号：US20150295085A1

    公开(公告)日：2015-10-15

    申请号：US14252147

    申请日：2014-04-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

    IPC: H01L29/78 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

    Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated method of formation. The transistor device has an epitaxial stack disposed over a semiconductor substrate, and a gate structure disposed over the epitaxial stack. A channel region extends below the gate structure between epitaxial source and drain regions located on opposing sides of the gate structure. First and second dislocation stress memorization (DSM) regions have a stressed lattice that generates stress within the channel region. The first and second DSM regions respectively extend from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region. Using the first and second DSM regions to stress the channel region, improves device performance.

    Abstract translation: 本公开涉及具有外延源极和漏极区域的晶体管器件，其具有向外延沟道区域提供应力的位错应力存储（DSM）区域和相关联的形成方法。 晶体管器件具有设置在半导体衬底上的外延层，以及设置在外延层上的栅极结构。 沟道区域在位于栅极结构的相对侧的外延源极和漏极区域之间的栅极结构的下方延伸。 第一和第二位错应力记忆（DSM）区域具有在沟道区域内产生应力的应力晶格。 第一和第二DSM区域分别从外延源区域的下面延伸到外延源区域内的从外延漏极区域下方的第一位置到外延漏极区域内的第二位置。 使用第一和第二DSM区域来压缩通道区域，提高了设备​​性能。

    RECESS AND EPITAXIAL LAYER TO IMPROVE TRANSISTOR PERFORMANCE
    13.
    发明申请
    RECESS AND EPITAXIAL LAYER TO IMPROVE TRANSISTOR PERFORMANCE 有权
    回收和外延层提高晶体管性能

    公开(公告)号：US20150263171A1

    公开(公告)日：2015-09-17

    申请号：US14208438

    申请日：2014-03-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yeh Hsu ,  Chia-Wen Liu ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Shih-Syuan Huang

    IPC: H01L29/78 ,  H01L21/263 ,  H01L29/66 ,  H01L21/306

    CPC classification number: H01L21/30604 ,  H01L21/28123 ,  H01L21/3065 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785

    Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.

    Abstract translation: 本公开的一些实施例涉及被配置为抵抗寄生耦合的半导体器件，同时保持对比较窄的晶体管的阈值电压控制。 在一些实施例中，形成在半导体衬底上的半导体器件。 半导体器件包括沟道，其包括在半导体衬底的表面上形成生长的外延层，以及形成在外延层上的栅极材料。 在一些实施例中，公开了一种形成半导体器件的方法。 该方法包括蚀刻半导体衬底的表面以在第一和第二隔离结构之间形成凹陷，在凹槽内形成外延层，其在半导体衬底的表面上形成生长，并在外延层上形成栅极材料。 还公开了其他实施例。

    EPITAXIAL CHANNEL WITH A COUNTER-HALO IMPLANT TO IMPROVE ANALOG GAIN
    14.
    发明申请
    EPITAXIAL CHANNEL WITH A COUNTER-HALO IMPLANT TO IMPROVE ANALOG GAIN 有权
    外来通道与计数器植入物提高模拟增益

    公开(公告)号：US20150200139A1

    公开(公告)日：2015-07-16

    申请号：US14156496

    申请日：2014-01-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

    IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L29/16

    CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

    Abstract: Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors.

    Abstract translation: 本公开的一些实施例涉及一种改善长沟道晶体管性能的植入物，对短沟道晶体管性能几乎没有影响。 为了减轻DIBL，衬底上的长沟道晶体管和短沟道晶体管都经历晕圈植入。 虽然光晕植入改善了短沟道晶体管的性能，但是它会降低长沟道晶体管的性能。 因此，仅在长沟道晶体管上执行反向注入才能恢复其性能。 为了实现这一点，反向注入以在长沟道晶体管的源极/漏极区附近引入掺杂剂杂质以抵消晕轮植入物的影响的角度进行，而反向晕轮植入物同时被遮蔽而达到 短沟道晶体管的通道。

    EPITAXIAL CHANNEL WITH A COUNTER-HALO IMPLANT TO IMPROVE ANALOG GAIN
    16.
    发明申请
    EPITAXIAL CHANNEL WITH A COUNTER-HALO IMPLANT TO IMPROVE ANALOG GAIN 有权
    外来通道与计数器植入物提高模拟增益

    公开(公告)号：US20160284800A1

    公开(公告)日：2016-09-29

    申请号：US15172417

    申请日：2016-06-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Yi-Ming Sheu

    IPC: H01L29/10 ,  H01L29/78 ,  H01L27/088

    CPC classification number: H01L29/1054 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/7833

    Abstract: The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.

    Abstract translation: 本公开涉及具有具有不同掺杂特性的沟道区的具有长沟道和短沟道晶体管的集成芯片。 在一些实施例中，集成芯片包括布置在具有第一长度的第一沟道区域上的第一栅极电极和布置在具有大于第一长度的第二长度的第二沟道区域上的第二栅电极。 第一沟道区域和第二沟道区域分别具有沿着第一长度和第二长度的掺杂剂分布，其掺杂浓度比边界高于第一沟道区和第二沟道区的中间。 掺杂剂浓度也比第一通道区域的边缘高于第二通道区域的边缘。

    Dislocation stress memorization technique (DSMT) on epitaxial channel devices
    17.
    发明授权
    Dislocation stress memorization technique (DSMT) on epitaxial channel devices 有权
    外延通道器件上的位错应力记忆技术（DSMT）

    公开(公告)号：US09419136B2

    公开(公告)日：2016-08-16

    申请号：US14252147

    申请日：2014-04-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsing Yu ,  Shih-Syuan Huang ,  Yi-Ming Sheu ,  Ken-Ichi Goto

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

    CPC classification number: H01L29/7847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/0603 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

    Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated method of formation. The transistor device has an epitaxial stack disposed over a semiconductor substrate, and a gate structure disposed over the epitaxial stack. A channel region extends below the gate structure between epitaxial source and drain regions located on opposing sides of the gate structure. First and second dislocation stress memorization (DSM) regions have a stressed lattice that generates stress within the channel region. The first and second DSM regions respectively extend from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region. Using the first and second DSM regions to stress the channel region, improves device performance.

    Abstract translation: 本公开涉及具有外延源极和漏极区域的晶体管器件，其具有向外延沟道区域提供应力的位错应力存储（DSM）区域和相关联的形成方法。 晶体管器件具有设置在半导体衬底上的外延层，以及设置在外延层上的栅极结构。 沟道区域在位于栅极结构的相对侧的外延源极和漏极区域之间的栅极结构的下方延伸。 第一和第二位错应力记忆（DSM）区域具有在沟道区域内产生应力的应力晶格。 第一和第二DSM区域分别从外延源区域的下面延伸到外延源区域内的从外延漏极区域下方的第一位置到外延漏极区域内的第二位置。 使用第一和第二DSM区域来压缩通道区域，提高了设备​​性能。

    COUNTER POCKET IMPLANT TO IMPROVE ANALOG GAIN
    19.
    发明申请
    COUNTER POCKET IMPLANT TO IMPROVE ANALOG GAIN 有权
    COUNTER POCKET IMPLANT提高模拟增益

    公开(公告)号：US20150243759A1

    公开(公告)日：2015-08-27

    申请号：US14222759

    申请日：2014-03-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Syuan Huang ,  Tsung-Hsing Yu ,  Yi-Ming Sheu

    IPC: H01L29/66 ,  H01L21/265 ,  H01L29/10

    CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A method for improving analog gain in long channel devices associated with a semiconductor workpiece is provided. A gate oxide layer is formed on the semiconductor workpiece, and a plurality of gate structures are formed over the gate oxide layer, wherein a first pair of the plurality of gate structures define a short channel device region and a second pair of the plurality of gate structures define a long channel device region. A first ion implantation with a first dopant is performed at a first angle, wherein the first dopant is one of an n-type dopant and a p-type dopant. A second ion implantation with a second dopant is performed at a second angle, wherein the second angle is greater than the first angle. The second dopant is one or an n-type dopant and a p-type dopant that is opposite of the first dopant, and a height of the plurality of gate structures and the second angle generally prevents the second ion implantation from implanting ions into the short channel device region.

    Abstract translation: 提供了一种用于改善与半导体工件相关联的长通道器件中的模拟增益的方法。 在半导体工件上形成栅极氧化层，并且在栅极氧化物层上形成多个栅极结构，其中多个栅极结构中的第一对限定短沟道器件区域和第二对多个栅极 结构定义了一个长通道器件区域。 以第一角度执行具有第一掺杂剂的第一离子注入，其中第一掺杂剂是n型掺杂剂和p型掺杂剂之一。 以第二角度执行具有第二掺杂剂的第二离子注入，其中第二角度大于第一角度。 第二掺杂剂是与第一掺杂剂相反的一种或n型掺杂剂和p型掺杂剂，并且多个栅极结构的高度和第二角度通常防止第二离子注入将离子注入到短路中 通道设备区域。

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