公开(公告)号：US11728254B2

公开(公告)日：2023-08-15

申请号：US16881211

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US11574872B2

公开(公告)日：2023-02-07

申请号：US16718219

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ting Lin ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/373 ,  H01L23/14 ,  H01L23/00 ,  H01L25/00

Abstract: Package structure and method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge die, and a second encapsulant. The first encapsulant laterally encapsulates the first die and the second die. The bridge die is electrically connected to the first die and the second die. The second encapsulant is located over the first die, the second die and the first encapsulant, laterally encapsulating the bridge die and filling a space between the bridge die and the first die, between the bridge die and the first encapsulant and between the bridge die and the second die. A material of the second encapsulant is different from a material of the first encapsulant.

公开(公告)号：US11557568B2

公开(公告)日：2023-01-17

申请号：US16801171

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L23/48

Abstract: A package includes at least one memory component and an insulating encapsulation. The at least one memory component includes a stacked memory structure and a plurality of conductive posts. The stacked memory structure is laterally encapsulated in a molding compound. The conductive posts are disposed on an upper surface of the stacked memory structure. The upper surface of the stacked memory structure is exposed from the molding compound. The insulating encapsulation encapsulates the at least one memory component. The top surfaces of the conductive posts are exposed form the insulating encapsulation. A material of the molding compound is different a material of the insulating encapsulation.

公开(公告)号：US20220384212A1

公开(公告)日：2022-12-01

申请号：US17884037

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chuan Chang ,  Szu-Wei Lu ,  Chen-Hua Yu

IPC: H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages. Corresponding structures result from these methods.

公开(公告)号：US11424174B2

公开(公告)日：2022-08-23

申请号：US17063143

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Pan ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.

公开(公告)号：US20220037229A1

公开(公告)日：2022-02-03

申请号：US16941509

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Chih-Chien Pan

IPC: H01L23/42 ,  H01L27/06 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die. The TIM is disposed on the first die, the second die, and the underfill layer. The adhesive pattern is disposed between the underfill layer and the TIM to separate the underfill layer from the TIM.

公开(公告)号：US11145562B2

公开(公告)日：2021-10-12

申请号：US16721829

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hua Chang ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes an interposer, a die and a conductive terminal. The interposer includes an encapsulant substrate, a through via and an interconnection structure. The through via is embedded in the encapsulant substrate. The interconnection structure is disposed on a first side of the encapsulant substrate and electrically connected to the through via. The die is electrically bonded to the interposer and disposed over the interconnection structure and the first side of the encapsulant substrate. The conductive terminal is disposed on a second side of the encapsulant substrate vertically opposite to the first side, and electrically connected to the interposer and the die.

公开(公告)号：US20210313304A1

公开(公告)日：2021-10-07

申请号：US16836927

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Pan ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/24 ,  H01L21/56 ,  G02B6/13

Abstract: A package structure and method of forming the same are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is laterally aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element insertion. The encapsulant laterally encapsulates the second die and the wall structure.

公开(公告)号：US20210225727A1

公开(公告)日：2021-07-22

申请号：US16745338

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer

公开(公告)号：US11056436B2

公开(公告)日：2021-07-06

申请号：US15175696

申请日：2016-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532

Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.